FullFlex

Document Number: 38-06082 Rev. *K

Page 2 of 52

Logic Block Diagram

The Logic Block Diagram for FullFlex72, FullFlex36, and FullFlex18 family follows: [1, 2, 3]

CONFIG Block

CONFIG Block

IO

Control

IO

Control

Address &

Counter Logic

Address &

Counter Logic

TRST

TMS

TDI

TDO

TCK

JTAG

MRST

RESET

LOGIC

Mailboxes

Collision Detection Logic

Dual Port Array

Notes

1. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and

CYD09S18V18 devices have 19 address bits. The CYD18S72V18 and CYD09S36V18 devices have 18 address bits. The CYD09S72V18 device has 17 address bits.

The CYD02S36V18 has 16 address bits.

2. The FullFlex72 family of devices has 72 data lines. The FullFlex36 family of devices has 36 data lines. The FullFlex18 family of devices has 18 data lines.

3. The FullFlex72 family of devices has eight byte enables. The FullFlex36 family of devices has four byte enables. The FullFlex18 family of devices has two byte enables.

[+] Feedback