HT82V42

Rev. 1.20

14

December 8, 2010

ACYCNRLC

Name

Description

0

Internal no force mux

Input mux, offset and gain registers determined by internal register bits

INTM1, INTM0.

1

Auto-cycling, no force mux

Input mux, offset and gain registers auto-cycled, RINP

® GINP ®

BINP

® RINP ¼ on RLC/ACYC pulse.

Colour Selection Description in Line-by-Line Mode

Operating Modes

Mode

Description

CDS

Max.

Sample

Rate

Sensor Interface

Description

Timing

Requirement

Register Contents

With CDS

Register Contents

Without CDS

1

Monochrome/Colour

Line-by-Line

Yes

5

MSPS

Only one input channel

at a time is

continuously sampled.

DCLK = 30MHz

DCLK: CDSCLK2

ratio is 6:1

SetReg1 : 3F(h)

SetReg1:

2D(h)

2

Fast Monochrome/

Colour Line-by-Line

Yes

10

MSPS

Identical to mode 1

DCLK = 30MHz

DCLK: CDSCLK2

ratio is 3:1

Identical to mode 1

plus SetReg3: bits 5:4

must be set to 0 (h)

Identical to

mode 1

3

Maximum speed

Monochrome/Colour

Line-by-Line

No

15

MSPS

Identical to mode 1

DCLK = 30MHz

DCLK: CDSCLK2

ratio is 2:1

CDS not possible

SetReg1:

6D(h)

4

Slow Monochrome/

Colour Line-by-Line

Yes

3.75

MSPS

Identical to mode 1

DCLK = 30MHz

DCLK: CDSCLK2

ratio is 2n:1, n>=4

Identical to mode 1

Identical to

mode 1

HT82V42 Operating Modes

Operating Mode Timing Diagrams

The following diagrams show 4-bit multiplexed output data and DCLK, CDSCLK2 and input video requirements for

most common operations as shown in Table.

Mode 1 Operation