HT82V42

Rev. 1.20

16

December 8, 2010

Device Configuration

The following table describes the location of each control bit used to determine the device operation. The register

map is programmed by writing the required codes to the appropriate address via the serial interface.

Address

Description

DEF

(h)

R/W

Bit

76

5

43210

000001 Setup Reg 1

0F

R/W

0

Mode3

PGAFS[1]

PGAFS[0]

1

1

CDS

EN

000010 Setup Reg 2

23

R/W

DEL[1]

DEL[0]

RLCDACRNG

0

VRLCEXT

INVOP

1

1

000011 Setup Reg 3

1F

R/W

0

0

CDSREF[1]

CDSREF[0]

RLVC[3]

RLVC[2]

RLVC[1]

RLVC[0]

000100 Software Reset

00

¾

¾¾

¾

¾¾¾¾¾

000101 Auto-cycle Reset

00

¾

¾¾

¾

¾¾¾¾¾

000110 Setup Reg 4

05

R/W

0

0

INTM[1]

INTM[0]

RLCINT

1

ACYCNRLC LINEBYLINE

000111 Revision Number

41

R

¾¾

¾

¾¾¾¾¾

001000 Setup Reg 5

00

R/W

0

0

0

PSENNEG

VDEL[2]

VDEL[1]

VDEL[0]

VSMPDET

001001 Setup Reg 6

00

R/W

ClkMotr

0

0

00000

001010 Reserved

01

R

0

0

0

00000

001011 Reserved

01

R

0

0

0

00000

001100 Reserved

01

R

0

0

0

00000

100000 Red Offset Value

80

R/W

RO[7]

RO[6]

RO[5]

RO[4]

RO[3]

RO[2]

RO[1]

RO[0]

100001 Green Offset Value

80

R/W

GO[7]

GO[6]

GO[5]

GO[4]

GO[3]

GO[2]

GO[1]

GO[0]

100010 Blue Offset Value

80

R/W

BO[7]

BO[6]

BO[5]

BO[4]

BO[3]

BO[2]

BO[1]

BO[0]

100011 RGB Offset Value

80

R/W

RGBO[7]

RGBO[6]

RGBO[5]

RGBO[4]

RGBO[3]

RGBO[2]

RGBO[1]

RGBO[0]

101000 Red PGA Gain

5C

R/W

RPGA[7]

RPGA[6]

RPGA[5]

RPGA[4]

RPGA[3]

RPGA[2]

RPGA[1]

RPGA[0]

101001 Green PGA Gain

5C

R/W

GPGA[7]

GPGA[6]

GPGA[5]

GPGA[4]

GPGA[3]

GPGA[2]

GPGA[1]

GPGA[0]

101010 Blue PGA Gain

5C

R/W

BPGA[7]

BPGA[6]

BPGA[5]

BPGA[4]

BPGA[3]

BPGA[2]

BPGA[1]

BPGA[0]

101011 RGB PGA Gain

5C

W

RGBPGA[7] RGBPGA[6]

RGBPGA[5]

RGBPGA[4] RGBPGA[3] RGBPGA[2] RGBPGA[1] RGBPGA[0]