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HT83B60 データシート(PDF) 13 Page - Holtek Semiconductor Inc |
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HT83B60 データシート(HTML) 13 Page - Holtek Semiconductor Inc |
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13 / 84 page ![]() Rev. 1.00 1� De�e��e� 1�� �011 Rev. 1.00 13 De�e��e� 1�� �011 HT83B60 Voice Mask MCU HT83B60 Voice Mask MCU System Architecture Akeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributed totheinternalsystemarchitecture.Therangeofdevicestakeadvantageoftheusualfeaturesfound withinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance. Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstruction executionareoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withthe exceptionofbranchorcallinstructions.An8-bitwideALUisusedinpracticallyalloperations oftheinstructionset.Itcarriesoutarithmeticoperations,logicoperations,rotation,increment, decrement,branchdecisions,etc.Theinternaldatapathissimplifiedbymovingdatathroughthe AccumulatorandtheALU.CertaininternalregistersareimplementedintheDataMemoryand canbedirectlyorindirectlyaddressed.Thesimpleaddressingmethodsoftheseregistersalong withadditionalarchitecturalfeaturesensurethataminimumofexternalcomponentsisrequiredto provideafunctionalI/Ocontrolsystemwithmaximumreliabilityandflexibility. Clocking and Pipelining Themainsystemclock,derivedfromeitheraCrystal,ERCorIRCoscillator,issubdividedinto fourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincrementedat thebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4 clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleforms oneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutive instructioncycles,thepipeliningstructureofthemicrocontrollerensuresthatinstructionsare effectivelyexecutedinoneinstructioncycle.Theexceptiontothisareinstructionswherethe contentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasethe instructionwilltakeonemoreinstructioncycletoexecute. Forinstructionsinvolvingbranches,suchasjumporcallinstructions,twomachinecyclesare requiredtocompleteinstructionexecution.Anextracycleisrequiredastheprogramtakesone cycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethe branch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintiming sensitiveapplications. Fe tc h In st . ( PC ) Ex ec ut e In st . (P C- 1) Fe tc h In st . (P C+ 1) Ex ec ut e In st . (P C) Fe tc h In st . (P C+ 2) Ex ec ut e In st . (P C+ 1) PC PC +1 PC +2 O sci ll at or C lo ck (S yst em C lo ck) P has e Cl o ck T 1 Pr og ra m C oun te r P has e Cl o ck T 2 P has e Cl o ck T 3 P has e Cl o ck T 4 Pi pe lin in g System Clocking and Pipelining |
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