 |
データシートサーチシステム |
|
|
データシートサーチシステム |
|
ADR02 データシート(PDF) 6 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADR02 データシート(HTML) 6 Page - Analog Devices |
|
|
6 / 44 page  AD5737 Data Sheet Rev. B | Page 6 of 44 AC PERFORMANCE CHARACTERISTICS AVDD = VBOOST_x = 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V; REFIN = 5 V; RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter1 Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE, CURRENT OUTPUT Output Current Settling Time 15 µs To 0.1% FSR, 0 mA to 24 mA range See Test Conditions/Comments ms For settling times when using the dc-to-dc con- verter, see Figure 25, Figure 26, and Figure 27 Output Noise (0.1 Hz to 10 Hz Bandwidth) 0.15 LSB p-p 12-bit LSB, 0 mA to 24 mA range Output Noise Spectral Density 0.5 nA/√Hz Measured at 10 kHz, midscale output, 0 mA to 24 mA range 1 Guaranteed by design and characterization; not production tested. TIMING CHARACTERISTICS AVDD = VBOOST_x = 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V; REFIN = 5 V; RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter1, 2, 3 Limit at TMIN, TMAX Unit Description t1 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min SYNC falling edge to SCLK falling edge setup time t5 13 ns min 24th/32nd SCLK falling edge to SYNC rising edge (see Figure 53) t6 198 ns min SYNC high time t7 5 ns min Data setup time t8 5 ns min Data hold time t9 20 µs min SYNC rising edge to LDAC falling edge (all DACs updated or any channel has digital slew rate control enabled) 5 µs min SYNC rising edge to LDAC falling edge (single DAC updated) t10 10 ns min LDAC pulse width low t11 500 ns max LDAC falling edge to DAC output response time t12 See Table 2 µs max DAC output settling time t13 10 ns min CLEAR high time t14 5 µs max CLEAR activation time t15 40 ns max SCLK rising edge to SDO valid t16 SYNC rising edge to DAC output response time (LDAC = 0) 21 µs min All DACs updated 5 µs min Single DAC updated t17 500 ns min LDAC falling edge to SYNC rising edge t18 800 ns min RESET pulse width t194 SYNC high to next SYNC low (digital slew rate control enabled) 20 µs min All DACs updated 5 µs min Single DAC updated 1 Guaranteed by design and characterization; not production tested. 2 All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V. 3 See Figure 3, Figure 4, Figure 5, and Figure 6. 4 This specification applies if LDAC is held low during the write cycle; otherwise, see t9. |
|
リンク URL |
| ALLDATASHEETはお客様のビジネスに役立ちますか？ [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | データシートへのリンク | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Japanese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
