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Data Sheet

AD5737

Rev. B | Page 21 of 44

THEORY OF OPERATION

The AD5737 is a quad, precision digital-to-current loop converter

designed to meet the requirements of industrial process control

applications. It provides a high precision, fully integrated, low cost,

single-chip solution for generating current loop outputs. The

current ranges available are 0 mA to 20 mA, 4 mA to 20 mA,

and 0 mA to 24 mA. The output configuration is user-selectable

via the DAC control register.

On-chip dynamic power control minimizes package power

dissipation (see the Dynamic Power Control section).

DAC ARCHITECTURE

The DAC core architecture of the AD5737 consists of two

matched DAC sections. A simplified circuit diagram is shown

in Figure 47. The four MSBs of the 12-bit data-word are decoded

to drive 15 switches, E1 to E15. Each switch connects one of

15 matched resistors either to ground or to the reference buffer

output. The remaining eight bits of the data-word drive Switch S0

to Switch S7 of an 8-bit voltage mode R-2R ladder network.

8-BIT R-2R LADDER

FOUR MSBs DECODED INTO

15 EQUAL SEGMENTS

E15

VOUT

Figure 47. DAC Ladder Structure

The voltage output from the DAC core is converted to a current,

which is then mirrored to the supply rail so that the application

sees only a current source output (see Figure 48). The current

outputs are supplied by VBOOST_x.

12-BIT

DAC

VBOOST_x

IOUT_x

RSET

Figure 48. Voltage-to-Current Conversion Circuitry

Reference Buffers

The AD5737 can operate with either an external or internal

reference. The reference input requires a 5 V reference for

specified performance. This input voltage is then buffered

before it is applied to the DAC.

POWER-ON STATE OF THE AD5737

When the AD5737 is first powered on, the IOUT_x pins are in

tristate mode. After a device power-on or a device reset, it is

recommended that the user wait at least 100 µs before writing to

the device to allow time for internal calibrations to take place.

SERIAL INTERFACE

The AD5737 is controlled by a versatile 3-wire serial interface

that operates at clock rates of up to 30 MHz and is compatible

with SPI, QSPI, MICROWIRE, and DSP standards. Data coding

is always straight binary.

Input Shift Register

The input shift register is 24 bits wide. Data is loaded into the

device MSB first as a 24-bit word under the control of the serial

clock input, SCLK. Data is clocked in on the falling edge of SCLK.

If packet error checking (PEC) is enabled, an additional eight

bits must be written to the AD5737, creating a 32-bit serial

interface (see the Packet Error Checking section).

The DAC outputs can be updated in one of two ways: individual

DAC updating or simultaneous updating of all DACs.

Individual DAC Updating

To update an individual DAC, LDAC is held low while data is

clocked into the DAC data register. The addressed DAC output

is updated on the rising edge of SYNC. See Table 3 and Figure 3

for timing information.

Simultaneous Updating of All DACs

To update all DACs simultaneously, LDAC is held high while

data is clocked into the DAC data register. After LDAC is taken

high, only the first write to the DAC data register of each channel

is valid; subsequent writes to the DAC data register are ignored,

although these subsequent writes are returned if a readback is

initiated. All DAC outputs are updated by taking LDAC low

after SYNC is taken high.

IOUT_x

DAC

INTERFACE

LOGIC

OUTPUT

AMPLIFIERS

LDAC

SDO

SDIN

12-BIT

DAC

VREFIN

SYNC

DAC DATA

OFFSET

AND GAIN

CALIBRATION

DAC INPUT

SCLK

Figure 49. Simplified Serial Interface of the Input Loading Circuitry

for One DAC Channel

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