ADDI9023

Data Sheet

Rev. 0 | Page 10 of 12

APPLICATIONS INFORMATION

POWER-UP SEQUENCE

When the ADDI9023 is powered up, the following sequence is

recommended (refer to Figure 7 for each step). Note that VH is

powered on before VL but, depending on CCD restrictions, VH

and VL can also be powered on simultaneously.

1. Turn on the VDD power supply, either 1.8 V or 3.3 V. After

VDD settles, the logic inputs from the timing generator (XV,

XSG, XSUBCK) can become active. Keep VDREN low during

this time.

2. Turn on the VH power supply, typically +12 V to +15 V.

3. Turn on the VL/VLL power supply, typically −6 V to −9 V.

4. Take the VDREN pin high to enable the V-driver outputs.

VDREN must remain high throughout normal vertical

timing operation.

POWER-DOWN SEQUENCE

When the ADDI9023 is powered down, reverse the procedure

shown in Figure 7.

1. Take the VDREN pin low to disable the V-driver outputs.

2. Turn off the VL/VLL and VH power supplies.

3. Turn off the VDD power supply.

0V

VH SUPPLY

VL, VLL SUPPLY

1

2

0V

VM

VH

VL/VLL (SUBCK ONLY)

XV, XSG,

XSUBCK

(INPUT)

VM

V-DRIVER OUTPUTS ACTIVE

WHEN VDREN IS HIGH

VDD

V1A TO V9

(OUTPUT)

VDREN

POWER

SUPPLIES

0V

0V

VDD

4

VDD

3

DON’T CARE

Figure 7. Recommended Power-Up Sequence