SC667201MMG3 datasheet(16/120 Pages) FREESCALE

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MPC5642A Microcontroller Data Sheet, Rev. 3.1

Freescale Semiconductor

Introduction

— Second time base counter can work as a continuous angle counter, enabling angle based applications to match

angle instead of time

— Both time bases can be exported to the eMIOS timer module

— Both time bases visible from the host

•

Event-triggered microengine:

— Fixed-length instruction execution in two-system-clock microcycle

— 14 KB of code memory (SCM)

— 3 KB of parameter (data) RAM (SPRAM)

— Parallel execution of data memory, ALU, channel control and flow control sub-instructions in selected

combinations

— 32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and subtraction, absolute value,

bitwise logical operations on 24-bit, 16-bit, or byte operands, single-bit manipulation, shift operations, sign

extension and conditional execution

— Additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned Multiply/MAC combinations,

and unsigned 24-bit divide. The MAC/Divide unit works in parallel with the regular microcode commands.

•

Resource sharing features support channel use of common channel registers, memory and microengine time:

— Hardware scheduler works as a “task management” unit, dispatching event service routines by predefined,

host-configured priority

— Automatic channel context switch when a “task switch” occurs, that is, one function thread ends and another

begins to service a request from other channel: channel-specific registers, flags and parameter base address are

automatically loaded for the next serviced channel

— SPRAM shared between host CPU and eTPU2, supporting communication either between channels and host or

inter-channel

— Hardware implementation of 4 semaphores support coherent parameter sharing between both eTPU engines

— Dual-parameter coherency hardware support allows atomic access to 2 parameters by host

•

Test and development support features:

— Nexus Class 1 debug, supporting single-step execution, arbitrary microinstruction execution, hardware

breakpoints and watchpoints on several conditions

— Software breakpoints

— SCM continuous signature-check built-in self test MISC (multiple input signature calculator), runs concurrently

with eTPU2 normal operation

1.5.13

Reaction module (REACM)

The REACM provides the ability to modulate output signals to manage closed loop control without CPU assistance. It works

in conjunction with the eQADC and eTPU2 to increase system performance by removing the CPU from the current control loop.

The REACM has the following features:

•

6 reaction channels with peak and hold control blocks

•

Each channel output is a bus of 3 signals, providing ability to control 3 inputs.

•

Each channel can implement a peak and hold waveform, making it possible to implement up to six independent peak

and hold control channels

Target applications include solenoid control for direct injection systems and valve control in automatic transmissions.

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