AFE5808A datasheet(62/66 Pages) TI1

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AFE5808A

SLOS729B – OCTOBER 2011 – REVISED APRIL 2012

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All bypassing and power supplies for the AFE5808A should be referenced to their corresponding ground planes.

All supply pins should be bypassed with 0.1µF ceramic chip capacitors (size 0603 or smaller). In order to

minimize the lead and trace inductance, the capacitors should be located as close to the supply pins as possible.

Where double-sided component mounting is allowed, these capacitors are best placed directly under the

package. In addition, larger bipolar decoupling capacitors 2.2µF to 10µF, effective at lower frequencies) may also

be used on the main supply pins. These components can be placed on the PCB in proximity (< 0.5 in or 12.7

mm) to the AFE5808A itself.

The AFE5808A has a number of reference supplies needed to be bypassed, such CM_BYP, VHIGH, and

VREF_IN. These pins should be bypassed with at least 1µF; higher value capacitors can be used for better low-

frequency noise suppression. For best results, choose low-inductance ceramic chip capacitors (size 0402, > 1µF)

and place them as close as possible to the device pins.

High-speed mixed signal devices are sensitive to various types of noise coupling. One primary source of noise is

the switching noise from the serializer and the output buffer/drivers. For the AFE5808A, care has been taken to

ensure that the interaction between the analog and digital supplies within the device is kept to a minimal amount.

The extent of noise coupled and transmitted from the digital and analog sections depends on the effective

inductances of each of the supply and ground connections. Smaller effective inductance of the supply and

ground pins leads to improved noise suppression. For this reason, multiple pins are used to connect each supply

and ground sets. It is important to maintain low inductance properties throughout the design of the PCB layout by

use of proper planes and layer thickness.

BOARD LAYOUT

Proper grounding and bypassing, short lead length, and the use of ground and power-supply planes are

particularly important for high-frequency designs. Achieving optimum performance with a high-performance

device such as the AFE5808A requires careful attention to the PCB layout to minimize the effects of board

parasitics and optimize component placement. A multilayer PCB usually ensures best results and allows

convenient component placement. In order to maintain proper LVDS timing, all LVDS traces should follow a

controlled impedance design. In addition, all LVDS trace lengths should be equal and symmetrical; it is

recommended to keep trace length variations less than 150mil (0.150 in or 3.81mm).

In addition, appropriate delay matching should be considered for the CW clock path, especially in systems with

high channel count. For example, if clock delay is half of the 16x clock period, a phase error of 22.5°C could

exist. Thus the timing delay difference among channels contributes to the beamformer accuracy.

Additional details on BGA PCB layout techniques can be found in the Texas Instruments Application Report

MicroStar BGA Packaging Reference Guide (SSYZ015B), which can be downloaded from www.ti.com.

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