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STGIPN3H60 データシート(PDF) 13 Page - STMicroelectronics |
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STGIPN3H60 データシート(HTML) 13 Page - STMicroelectronics |
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13 / 21 page ![]() STGIPN3H60 Electrical characteristics Doc ID 018957 Rev 3 13/21 3.2 Waveform definitions Figure 5. Dead time and interlocking waveform definitions LIN HIN LVG HVG LIN HIN LVG HVG LIN HIN LVG HVG LIN HIN LVG HVG DTLH DTHL DTLH DTHL DTLH DTHL DTLH DTHL gate driver outputs OFF (HALF-BRIDGE TRI-STATE) CONTROL SIGNAL EDGES OVERLAPPED: INTERLOCKING + DEAD TIME CONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIME CONTROL SIGNALS EDGES NOT OVERLAPPED, BUT INSIDE THE DEAD TIME: DEAD TIME CONTROL SIGNALS EDGES NOT OVERLAPPED, OUTSIDE THE DEAD TIME: DIRECT DRIVING (*) HIN and LIN can be connected together and driven by just one control signal gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) |
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