V3p3

V3p3

(1)

(2)

EN_BCKx

BUCKENABLE

6uA

Enable

Threshold

BUCK A

Enable

BUCKB

Enable

BUCKC

Enable

Time

Delaytime = 0.2ms/nF

1.2V

(1) Connect EN_BCKx pin to V3P3 to follow the default power-up sequence or

(2) Connect a capacitor from EN_BCKx to GND to generate a custom power-up sequence.

TPS65232

SLVSA42 – FEBRUARY 2010

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SOFT START (BUCK1, 2, and 3)

Soft start current source

2

mA

Soft start ramp voltage

Ramp end

0.8

V

Soft start capacitor

2

3.3

4.7

nF

SSDONE_BK

Deglitch time

2.5

ms

SSDONE_DCH

SS discharge time

500

ms

THERMAL SHUTDOWN

Thermal warning

120

°C

Thermal s/d trip point

160

°C

Thermal s/d hysteresis

20

°C

POWER-UP SEQUENCING

ON/OFF control and power sequencing of the three buck regulators is controlled through EN_BCK1, EN_BCK2,

and EN_BCK3 enable pins. Each pin is internally connected to a 6-mA constant-current source and monitored by

a comparator with Schmitt trigger input with defined threshold. Connecting EN_BCKn pin to ground disables

BUCKn and connecting EN_BCKn to V3p3 will enable the respective buck without delay. If more than one buck

enable pin is connected to V3p3 the default startup sequence is BUCK1, BUCK2, BUCK3 and the minimum

startup delay between rails is the soft-start time (typical 1.5 ms) plus 1 ms.

To create a startup-sequence different from the default, capacitors are connected between the EN_BUCKn pins

and ground. At power-up the capacitors are first discharged and then charged to V3p3 level by internal current

sources (6 mA typical) creating a constant-slope voltage ramp. A regulator is enabled when its EN pin voltage

crosses the enable threshold (typical 1.2 V). A delay of 0.2 ms is generated for each 1-nF of capacitance

connected to the enable pin. If two enable pins are pulled high while the third regulator is starting up, the default

sequence will be applied to enable the remaining two regulators. To override default power-up sequence it is

recommended that delay times differ by more than the soft-start time (typical 1.3 ms) plus 1 ms.

Figure 1. Customizing the Power-Up Sequence

10

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