SST30VR021 datasheet(8/12 Pages) SST

部品番号	SST30VR021

部品情報	2 Mbit ROM 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo

PDF	12 Pages

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メーカー	SST [Silicon Storage Technology, Inc]

ホームページ	http://www.sst.com/

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8 / 12 page

Data Sheet

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM

ROM/RAM Combo

SST30VR021 / SST30VR022 / SST30VR023

S71135-02-000

4/01

380

FIGURE

6: SRAM READ CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED) (OE# = RAMCS# = VIL, WE# = VIH)

FIGURE 7: SRAM READ CYCLE TIMING DIAGRAM (OE# OR RAMCS# CONTROLLED)

TRC

TAA

Data Valid

380 ILL F04.0

Data Out

Previous Data Valid

Address

TOH

TRC

TAA

TOE

TCO

TLZ(2)

TOH

TOHZ(1)

THZ (1,2)

Data Valid

380 ILL F05.0

Data Out

RAMCS#

High-Z

Address

OE#

Notes: 1. THZ and TOHZ are defined as the time at which the outputs achieve the open circuit condition

and are referenced to the VOH or VOL.

2. At any given temperature and voltage condition THZ(max) is less than TLZ(min) both for a given

device and from device to device.

3. WE# is high for Read cycle.

4. Address valid prior to coincidence with RAMCS# transition low.

SST30VR021 データシート(PDF) 8 Page - Silicon Storage Technology, Inc

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