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CDCLVC1310 データシート(PDF) 9 Page - Texas Instruments

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部品番号 CDCLVC1310
部品情報  Ten-Output Low-Jitter Low-Power Clock Buffer
PDF  28 Pages
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI1 - Texas Instruments

CDCLVC1310 データシート(HTML) 9 Page - Texas Instruments

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CDCLVC1310
www.ti.com
SCAS917B
– JULY 2011 – REVISED FEBRUARY 2012
PHASE NOISE WITH XTAL
(1) SELECTED
VDD = VDDO = 2.5 V/3.3V, fXTAL = 25 MHz, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IB = 12 kHz to 5 MHz, VDD = VDDO
80
= 3.3 V
Jrms
RMS phase jitter
ps rms
IB = 12 kHz to 5 MHz, VDD = VDDO
115
= 2.5 V
foffset = 100 Hz, VDD = VDDO = 3.3
–92
V
foffset = 1 kHz, VDD = VDDO = 3.3 V
–137
foffset = 10 kHz, VDD = VDDO = 3.3
–163
V
foffset = 100 kHz, VDD = VDDO = 3.3
–168
V
foffset = 1 MHz, VDD = VDDO = 3.3
–168
V
foffset = 5 MHz, VDD = VDDO = 3.3
–169
V
PN
Phase noise (see Figure 15)
dBc/Hz
foffset = 100 Hz, VDD = VDDO = 2.5
–91
V
foffset = 1 kHz, VDD = VDDO = 2.5 V
–136
foffset = 10 kHz, VDD = VDDO = 2.5
–159
V
foffset = 100 kHz, VDD = VDDO = 2.5
–164
V
foffset = 1 MHz, VDD = VDDO = 2.5
–165
V
foffset = 5 MHz, VDD = VDDO = 2.5
–165
V
(1)
Crystal specification: CL = 18 pF; ESR = 35 Ω (max); C0 = 7 pF; drive level = 100 µW (max)
DEVICE CURRENT CONSUMPTION
over recommended ranges of supply voltage, load and ambient temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OVERALL PARAMETERS FOR ALL VERSIONS
OE = 0 V or VDD;
Ref. input (PRI/SEC) = 0 V or VDD;
14
IO = 0 mA; VDD/VDDO = 3.3 V
IDD
Static device current(1)
mA
OE = 0 V or VDD;
Ref. input (PRI/SEC) = 0 V or VDD;
8
IO = 0 mA; VDD/VDDO = 2.5 V
IDD,XTAL
Device current with XTAL input(1)
20
mA
VDDO = 3.465 V; f = 100 MHz
8.8
VDDO = 2.625 V; f = 100 MHz
7.7
Power dissipation capacitance per
CPD
pF
output(2)
VDDO = 2 V; f = 100 MHz
7.3
VDDO = 1.65 V; f = 100 MHz
6.9
(1)
IDD and IDD,XTAL is the current through VDD; outputs on or in the high-impedance state; no load.
(2)
This is the formula for the power dissipation calculation (see Power Consideration section)
IDD,Total = IDD + IDD,Cload + IDD,dyn [mA]
IDD,dyn = CPD × VDDO × f × n [mA]
IDD,Cload = Cload × VDDO × f × n [mA]
n = Number of switching output pins
Copyright
© 2011–2012, Texas Instruments Incorporated
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9
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