CDCLVC1310

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SCAS917B

– JULY 2011 – REVISED FEBRUARY 2012

Figure 14. Phase Noise Profile With 25-MHz Crystal at Nominal Conditions

System-Level Additive Jitter Measurement

For high-performance devices, phase-noise measurements are influenced by limitations of the equipment. The

noise floor of the equipment often exceeds the noise floor of the device. The real noise floor of the device is

probably lower (see LVCMOS Output Characteristics). Phase noise is influenced by the input source and the

measurement equipment. Additional measurements and information about system-level additive jitter and noise

floor are available in the applications report Phase Noise Performance of CDCLVC1310 (SCAA115).

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