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CXD3003 データシート(PDF) 77 Page - Sony Corporation |
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CXD3003 データシート(HTML) 77 Page - Sony Corporation |
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77 / 137 page ![]() – 77 – CXD3003R Timing Chart 4-3 Normal-speed PB 400 to 500ns RFCK MNT3 MNT1 MNT0 t = Dependent on error condition C1 correction C2 correction Strobe Strobe MNT2 §4-4. DA Interface • The CXD3003R has two DA interface modes. a) 48-bit slot interface This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. b) 64-bit slot interface This interface includes 64 cycles of the bit clock within one LRCK cycle, and is LSB first. When LRCK is low, the data is for the left channel. |
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