SPC560P60L3 datasheet(24/104 Pages) STMICROELECTRONICS

24 / 104 page

Introduction

SPC56xP54x, SPC56xP60x

24/104

Doc ID 18340 Rev 3

It implements the following features:

●

Double buffered trigger generation unit with up to eight independent triggers generated

from external triggers

●

Trigger generation unit configurable in sequential mode or in triggered mode

●

Each Trigger can be appropriately delayed to compensate the delay of external low

pass filter

●

Double buffered global trigger unit allowing eTimer synchronization and/or ADC

command generation

●

Double buffered ADC command list pointers to minimize ADC-trigger unit update

●

Double buffered ADC conversion command list with up to 24 ADC commands

●

Each trigger has the capability to generate consecutive commands

●

ADC conversion command allows to control ADC channel from each ADC, single or

synchronous sampling, independent result queue selection

1.5.26

Cyclic redundancy check (CRC)

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3 contexts for the concurrent CRC computation

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Separate CRC engine for each context

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Zero-wait states during the CRC computation (pipeline scheme)

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3 hard-wired polynomials (CRC-8 VDA CAN, CRC-32 ethernet and CRC-16-CCITT)

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Support for byte/half-word/word width of the input data stream

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Support for expected and actual CRC comparison

1.5.27

Nexus development interface (NDI)

The NDI block provides real-time development support capabilities for the SPC56xP54/60

Power Architecture based MCU in compliance with the IEEE-ISTO 5001-2003 standard.

This development support is supplied for MCUs without requiring external address and data

pins for internal visibility. The NDI block is an integration of several individual Nexus blocks

that are selected to provide the development support interface for this device. The NDI block

interfaces to the host processor and internal buses to provide development support as per

the IEEE-ISTO 5001-2003 Class 2+ standard. The development support provided includes

access to the MCU’s internal memory map and access to the processor’s internal registers

during run time.

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