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SPIRIT1 データシート(PDF) 81 Page - STMicroelectronics |
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SPIRIT1 データシート(HTML) 81 Page - STMicroelectronics |
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81 / 94 page ![]() SPIRIT1 Register table Doc ID 022758 Rev 3 81/94 PCKTCTRL1 0x33 7:5 CRC_MODE[2:0] 001 R/W CRC: 0: No CRC, 1: 0x07, 2: 0x8005, 3: 0x1021, 4: 0x864CBF 4WHIT_EN[0] 0 1: enable the whitening mode on the data 3:2 TXSOURCE[1:0] 00 TX source data: 0: normal mode, 1: direct through FIFO, 2: direct through GPIO, 3: PN9 1 Reserved 0 0FEC_EN 0 1: enable the FEC encoding in TX or enable the Viterbi decoding in RX PCKTLEN1 0x34 7:0 PCKTLEN1 0 R/W Length of packet in bytes (MSB) PCKTLEN0 0x35 7:0 PCKTLEN0 0x14 R/W Length of packet in bytes (LSB) SYNC4 0x36 7:0 SYNC4 0x88 R/W Sync word 4 SYNC3 0x37 7:0 SYNC3 0x88 R/W Sync word 3 SYNC2 0x38 7:0 SYNC2 0x88 R/W Sync word 2 SYNC1 0x39 7:0 SYNC1 0x88 R/W Sync word 1 QI 0x3A 7:6 SQI_TH[1:0] 00 R/W SQI threshold (see Section 9.10.5) 5:2 PQI_TH[3:0] 0000 PQI threshold (see Section 9.10.4) 1 SQI_EN[0] 1 1: enable SQI 0 PQI_EN[0] 0 1: enable PQI MBUS_PRMBL 0x3B 7:0 MBUS_PRMBL[7:0] 0x20 R/W MBUS preamble length in chip sequence ‘01’ MBUS_PSTMBL 0x3C 7:0 MBUS_PSTMBL[7:0] 0x20 R/W MBUS postamble length in chip sequence ‘01’ Table 40. Packet/protocol configuration registers (continued) Register name Address Bit Field Name Reset R/W Description |
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