SPIRIT1 datasheet(30/94 Pages) STMICROELECTRONICS

30 / 94 page

Operating modes

SPIRIT1

30/94

Doc ID 022758 Rev 3

The commands are immediately valid after SPI transfer completion (i.e. no need for any CSn

positive edge).

7.1

Reset sequence

SPIRIT1 is provided with an automatic power-on reset (POR) circuit which generates an

internal RESETN active (low) level for a time TRESET after the VDD reaches the reset

release threshold voltage VRRT (provided that SDN is low), as shown below. The same reset

pulse is generated after a step-down on the input pin SDN (provided that VDD>VRRT).

Figure 4.

Power-on reset timing and limits

The parameters VRRT and TRESET are fixed by design. At RESET, all the registers are

initialized to their default values. Typical and extreme values are reported in the following

table.

0x6D

AES KeyDec

All

Compute the key and start decryption

0x70

SRES

All

Reset

0x71

FLUSHRXFIFO

All

Clean the RX FIFO

0x72

FLUSHTXFIFO

All

Clean the TX FIFO

Table 18.

Commands list (continued)

Command

code

Command name

Execution state

Description

Table 19.

POR parameters

Symbol

Parameter

Min.

Typ.

Max.

Unit

VRRT

Reset startup threshold voltage

0.5

TRESET

Reset pulse width

0.24

0.65

1.0

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