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SPEAR320 データシート(PDF) 21 Page - STMicroelectronics

部品番号 SPEAR320
部品情報  Embedded MPU with ARM926 core, optimized for factory automation and consumer applications
PDF  73 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPEAR320 データシート(HTML) 21 Page - STMicroelectronics

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SPEAr320
Architecture overview
Doc ID 16755 Rev 5
21/73
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Slave bulk transfer mode
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Ignores CBUS addresses (predessor to I2C that used to share the I2C bus)
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Transmit and receive buffers
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Interrupt or polled-mode operation
●
Handles bit and byte waiting at all bus speeds
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Digital filter for the received SDA and SCL lines
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Handles component parameters for configurable software driver support
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Supports APB data bus widths of 8, 16 and 32 bits.
3.18
UARTs
The SPEAr320 has 3 UARTs with different capabilities.
3.18.1
UART0
Main features:
●
Separate 16 x 8 (16 locations deep x 8-bit wide) transmit and 16 x 12 receive FIFOs to
reduce CPU interrupts
●
Speed up to 3 Mbps
●
Hardware and/or software flow control
●
Modem interface signals
3.18.2
UART1
Main features:
●
Separate 16 x 8 (16 location deep x 8-bit wide) transmit and 16x12 receive FIFOs to
reduce CPU interrupts
●
Speed up to 7 Mbps
●
Hardware flow control (in Small Printers and Automation Expansion modes only) and/or
software flow control
3.18.3
UART2
Main features:
●
Separate 16x8 (16 location deep x 8-bit wide) transmit and 16x12 receive FIFOs to
reduce CPU interrupts
●
Speed up to 7 Mbps
●
Software flow control
3.19
JPEG CODEC
SPEAr320 provides a JPEG CODEC with header processing (JPGC), able to decode (or
encode) image data contained in the SPEAr320 RAM, from the JPEG (or MCU) format to
the MCU (or JPEG) format.



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