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4256BWP データシート(PDF) 8 Page - STMicroelectronics |
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4256BWP データシート(HTML) 8 Page - STMicroelectronics |
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8 / 41 page  Signal description M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF 8/41 Doc ID 6757 Rev 28 2 Signal description 2.1 Serial Clock (SCL) The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data on SDA(out). 2.2 Serial Data (SDA) SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull-up resistor must be connected from Serial Data (SDA) to VCC (Figure 12 indicates how to calculate the value of the pull-up resistor). 2.3 Chip Enable (E2, E1, E0) (E2,E1,E0) input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code (see Table 2). These inputs must be tied to VCC or VSS, as shown in Figure 4. When not connected (left floating), these inputs are read as low (0). Figure 4. Device select code 2.4 Write Control (WC) This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either driven low or left floating. When Write Control (WC) is driven high, device select and address bytes are acknowledged, Data bytes are not acknowledged. 2.5 VSS (ground) VSS is the reference for the VCC supply voltage. Ai12806 VCC M24xxx VSS Ei VCC M24xxx VSS Ei |
同様の部品番号 - 4256BWP |
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同様の説明 - 4256BWP |
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