WM8978CGEFLSLASHV datasheet(74/118 Pages) WOLFSON

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WM8978

Production Data

PD, Rev 4.5, October 2011

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Clock

Generation

Control

Sets the chip to be master over LRC and

BCLK

0=BCLK and LRC clock are inputs

1=BCLK and LRC clock are outputs

generated by the WM8978 (MASTER)

4:2

BCLKDIV

000

Configures the BCLK output frequency,

for use when the chip is master over

BCLK.

000=divide by 1 (BCLK=SYSCLK)

001=divide by 2 (BCLK=SYSCLK/2)

010=divide by 4

011=divide by 8

100=divide by 16

101=divide by 32

110=reserved

111=reserved

7:5

MCLKDIV

010

Sets the scaling for either the MCLK or

PLL clock output (under control of

CLKSEL)

000=divide by 1

001=divide by 1.5

010=divide by 2

011=divide by 3

100=divide by 4

101=divide by 6

110=divide by 8

111=divide by 12

CLKSEL

Controls the source of the clock for all

internal operation:

0=MCLK

1=PLL output

Table 54 Clock Control

The CLKSEL bit selects the internal source of the Master clock from the PLL (CLKSEL=1) or from

MCLK (CLKSEL=0). When the internal clock is switched from one source to another using the

CLKSEL bit, the clock originally selected must generate at least one falling edge after CLKSEL has

changed for the switching of clocks to be successful.

EXAMPLE:

If the PLL is the current source of the internal clock (CLKSEL=1) and it is required to switch to the

MCLK, change CLKSEL to select MCLK (CLKSEL=0) and then disable PLL (PLLEN=0).

WM8978CGEFL/V データシート(PDF) 74 Page - Wolfson Microelectronics plc

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