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AD9525/PCBZ データシート(PDF) 41 Page - Analog Devices

部品番号 AD9525/PCBZ
部品情報  Low Jitter Clock Generator with Eight LVPECL Outputs
PDF  48 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD9525/PCBZ データシート(HTML) 41 Page - Analog Devices

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Data Sheet
AD9525
Rev. 0 | Page 41 of 48
Table 41. LVPECL Drivers OUT2
Reg.
Addr.
(Hex)
Bits
Bit Name
Description
0x0F2
[7:5]
Don’t care
Don’t care
4
Power down
Channel 2 and
Channel 3
Powers down Channel 2 and Channel 3
0: enabled (default)
1: power-down
3
Don’t care
Don’t care
[2:1]
OUT2 level
Bit 1
Bit 0
VOD (mV)
0
0
400
0
1
600
1
0
780 (default)
1
1
960
0
OUT2 driver
power-down
0: enabled (default)
1: power-down
Table 42. LVPECL Drivers OUT3
Reg.
Addr.
(Hex)
Bits
Bit Name
Description
0x0F3
[7:5]
Don’t care
Don’t care
4
Reserved
Reserved, write 0
3
Don’t care
Don’t care
[2:1]
OUT3 level
Bit 1
Bit 0
VOD (mV)
0
0
400
0
1
600
1
0
780 (default)
1
1
960
0
OUT3 driver
power-down
0: enabled (default)
1: power-down
Table 43. PECL Drivers OUT4
Reg.
Addr.
(Hex)
Bits
Bit Name
Description
0x0F4
[7:5]
Don’t care
Don’t care
4
Power down
Channel 4 and
Channel 5
Powers down Channel 4 and Channel 5
0: enabled (default)
1: power-down
3
Don’t care
Don’t care
[2:1]
OUT4 level
Bit 1
Bit 0
VOD (mV)
0
0
400
0
1
600
1
0
780 (default)
1
1
960
0
OUT4 driver
power-down
0: enabled (default)
1: power-down



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