REV. 0

AD7664

–14–

DIGITAL INTERFACE

The AD7664 has a versatile digital interface; it can be interfaced

with the host system by using either a serial or parallel interface.

The serial interface is multiplexed on the parallel data bus. The

AD7664 digital interface also accommodates both 3 V or 5 V logic

by simply connecting the OVDD supply pin of the AD7664 to

the host system interface digital supply. Finally, by using the

OB/

2C input pin, both two’s complement or straight binary

coding can be used.

The two signals

CS and RD control the interface. CS and RD

have a similar effect because they are OR’d together internally.

When at least one of these signals is high, the interface outputs

are in high impedance. Usually,

CS allows the selection of each

AD7664 in multicircuits applications and is held low in a single

AD7664 design.

RD is generally used to enable the conversion

result on the data bus.

CNVST

BUSY

DATA

BUS

CS = RD = 0

PREVIOUS CONVERSION DATA

NEW DATA

Figure 13. Master Parallel Data Timing for Reading

(Continuous Read)

PARALLEL INTERFACE

The AD7664 is configured to use the parallel interface when the

SER/

PAR is held low. The data can be read either after each

conversion, which is during the next acquisition phase, or dur-

ing the following conversion as shown, respectively, in Figure 14

and Figure 15. When the data is read during the conversion,

however, it is recommended that it is read only during the first

half of the conversion phase. That avoids any potential feed-

through between voltage transients on the digital interface and

the most critical analog conversion circuitry.

CURRENT

CONVERSION

BUSY

DATA

BUS

CS

RD

Figure 14. Slave Parallel Data Timing for Reading

(Read After Convert)

PREVIOUS

CONVERSION

CS = 0

CNVST,

RD

BUSY

DATA

BUS

Figure 15. Slave Parallel Data Timing for Reading

(Read During Convert)

SERIAL INTERFACE

The AD7664 is configured to use the serial interface when the

SER/

PAR is held high. The AD7664 outputs 16 bits of data,

MSB first, on the SDOUT pin. This data is synchronized with

the 16 clock pulses provided on SCLK pin. The output data is

valid on both the rising and falling edge of the data clock.

MASTER SERIAL INTERFACE

Internal Clock

The AD7664 is configured to generate and provide the serial data

clock SCLK when the EXT/

INT pin is held low. The AD7664

also generates a SYNC signal to indicate to the host when the

serial data is valid. The serial clock SCLK and the SYNC signal

can be inverted if desired. Depending on RDC/SDIN input, the

data can be read after each conversion or during the following

conversion. Figure 16 and Figure 17 show the detailed timing

diagrams of these two modes.

Usually, because the AD7664 is used with a fast throughput, the

mode master, read during conversion is the most recommended

serial mode when it can be used.

In read-during-conversion mode, the serial clock and data toggle

at appropriate instants which minimize potential feedthrough

between digital activity and the critical conversion decisions.

In read-after-conversion mode, it should be noted that, unlike in

other modes, the signal BUSY returns low after the 16 data bits

are pulsed out and not at the end of the conversion phase which

results in a longer BUSY width.

SLAVE SERIAL INTERFACE

External Clock

The AD7664 is configured to accept an externally supplied

serial data clock on the SCLK pin when the EXT/

INT pin is

held high. In this mode, several methods can be used to read the

data. When

CS and RD are both low, the data can be read after

each conversion or during the following conversion. The exter-

nal clock can be either a continuous or discontinuous clock. A

discontinuous clock can be either normally high or normally low

when inactive. Figure 18 and Figure 20 show the detailed tim-

ing diagrams of these methods.