REV. 0

AD7664

–16–

While the AD7664 is performing a bit decision, it is important

that voltage transients not occur on digital input/output pins or

degradation of the conversion result could occur. This is par-

ticularly important during the second half of the conversion

phase because the AD7664 provides error correction circuitry

that can correct for an improper bit decision made during the

first half of the conversion phase. For this reason, it is recom-

mended that when an external clock is being provided, it is a

discontinuous clock that is toggling only when BUSY is low or,

more importantly, that is does not transition during the latter

half of BUSY high.

External Discontinuous Clock Data Read After Conversion

Though the maximum throughput cannot be achieved using this

mode, it is the most recommended of the serial slave modes.

Figure 18 shows the detailed timing diagrams of this method.

After a conversion is complete, indicated by BUSY returning

low, the result of this conversion can be read while both

CS and

RD are low. The data is shifted out, MSB first, with 16 clock

pulses and is valid on both rising and falling edge of the clock.

Among the advantages of this method, the conversion perfor-

mance is not degraded because there are no voltage transients

on the digital interface during the conversion process.

Another advantage is to be able to read the data at any speed up

to 40 MHz which accommodates both slow digital host interface

and the fastest serial reading.

Finally, in this mode only, the AD7664 provides a “daisy chain”

feature using the RDC/SDIN input pin for cascading multiple

converters together. This feature is useful for reducing component

count and wiring connections when desired as, for instance, in

isolated multiconverter applications.

An example of the concatenation of two devices is shown in

Figure 19. Simultaneous sampling is possible by using a com-

mon

CNVST signal. It should be noted that the RDC/SDIN

input is latched on the opposite edge of SCLK of the one used to

shift out the data on SDOUT. Hence, the MSB of the “upstream”

converter just follows the LSB of the “downstream” converter

on the next SCLK cycle.

SCLK

SDOUT

D15

D14

D1

D0

D13

X15

X14

X13

X1

X0

Y15

Y14

CS, RD

BUSY

SDIN

EXT/I

NT = 1

INVSCLK = 0

X15

X14

X

1

2

3

14

151617

18

Figure 18. Slave Serial Data Timing for Reading (Read After Convert)

CNVST

CS

SCLK

SDOUT

RDC/SDIN

BUSY

BUSY

DATA

OUT

AD7664

#1

(DOWNSTREAM)

BUSY

OUT

CNVST

CS

SCLK

AD7664

#2

(UPSTREAM)

RDC/SDIN

SDOUT

SCLK IN

CS IN

CNVST IN

Figure 19. Two AD7664s in a “Daisy Chain” Configuration

External Clock Data Read During Conversion

Figure 20 shows the detailed timing diagrams of this method.

During a conversion, while both

CS and RD are both low, the

result of the previous conversion can be read. The data is shifted

out, MSB first, with 16 clock pulses and is valid on both rising and

falling edge of the clock. The 16 bits have to be read before the

current conversion is complete. If that is not done, RDERROR is

pulsed high and can be used to interrupt the host interface to

prevent incomplete data reading. There is no “daisy chain”

feature in this mode and RDC/SDIN input should always be

tied either high or low.

To reduce performance degradation due to digital activity, a fast

discontinuous clock of, at least 18 MHz, when impulse mode is

used, 25 MHz when normal mode is used or 40 MHz when warp

mode is used, is recommended to ensure that all the bits are read

during the first half of the conversion phase. It is also possible

to begin to read the data after conversion and continue to read

the last bits even after a new conversion has been initiated. That

allows the use of a slower clock speed like 14 MHz in impulse

mode, 18 MHz in normal mode and 25 MHz in warp mode.