AOZ1052PI datasheet(10/14 Pages) AOSMD

10 / 14 page

AOZ1052PI

Rev. 0.5 September 2012

www.aosmd.com

Page 10 of 14

The zero given by the external compensation network,

capacitor CC and resistor RC, is located at:

To design the compensation circuit, a target crossover

frequency fC to close the loop must be selected. The

system crossover frequency is where the control loop

has unity gain. The crossover is the also called the

converter bandwidth. Generally a higher bandwidth

means faster response to load transients. However, the

bandwidth should not be too high because of system

stability concern. When designing the compensation

loop, converter stability under all line and load condition

must be considered.

Usually, it is recommended to set the bandwidth to be

equal or less than 1/10 of the switching frequency.

The strategy for choosing RC and CC is to set the cross

over frequency with RC and set the compensator zero

with CC. Using selected crossover frequency, fC, to

calculate RC:

where;

fC is the desired crossover frequency. For best performance,

fC is set to be about 1/10 of the switching frequency;

VFB is 0.8V,

GEA is the error amplifier transconductance, which is

200 x 10-6A/V, and

GCS is the current sense circuit transconductance, which is

8A/V

The compensation capacitor CC and resistor RC together

make a zero. This zero is put somewhere close to the

dominate pole fp1 but lower than 1/5 of the selected

crossover frequency. CC can is selected by:

The above equation can be simplified to:

An easy-to-use application software which helps to

design and simulate the compensation loop can be found

at www.aosmd.com.

Thermal Management and Layout

Considerations

In the AOZ1052PI buck regulator circuit, high pulsing

current flows through two circuit loops. The first loop

starts from the input capacitors, to the VIN pin, to the

LX pad, to the filter inductor, to the output capacitor and

load, and then returns to the input capacitor through

ground. Current flows in the first loop when the high side

switch is on. The second loop starts from the inductor,

to the output capacitors and load, to the low side

NMOSFET. Current flows in the second loop when the

low side NMOSFET is on.

In PCB layout, minimizing the area of the two loops will

reduce the noise of the circuit and improves efficiency.

A ground plane is strongly recommended to connect the

input capacitor, the output capacitor, and the PGND pin

of the AOZ1052PI.

In the AOZ1052PI buck regulator circuit, the major power

dissipating components are the AOZ1052PI and the

output inductor. The total power dissipation of converter

circuit can be measured by input power minus output

power:

The power dissipation of the inductor can be

approximately calculated by the output current and DCR

value of the inductor:

The actual junction temperature can be calculated by the

power dissipation in the AOZ1052PI and the thermal

impedance from junction to ambient:

The maximum junction temperature of the AOZ1052PI is

150ºC, which limits the maximum load current capability.

Please see the thermal de-rating curves for maximum

load current of the AOZ1052PI under different ambient

temperature.

The thermal performance of the AOZ1052PI is strongly

affected by the PCB layout. Care should be taken during

the design process to ensure that the IC will operate

under the recommended environmental conditions.

fZ2

 C



-----------------------------------

VFB

----------

 C



GEA GCS



------------------------------



1.5

 R

fP1



-----------------------------------

CO RL



---------------------

Ptotal_loss

VIN IIN VO IO



–



Pinductor_loss IO2 Rinductor 1.1



Tjunction

Ptotal_loss Pinductor_loss

–

 



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