P26/29

Rev. M, May 2010

ML5012

6-4. Indication of end of comparison

At the end of A/D conversion the bit S/S and bit EN are cleared. Monitoring one of these bits detects the

end of comparison.

There is an external pin (PADEOC) to indicate the end of conversion. When the conversion is completed,

an “H” pulse signal will be outputted to this pin.

6-5. Storing comparison result

The result of comparison sets the bit RSLT of A/D configuration register to either ‘1‘ or ‘0’ depending on

the level of the input voltages as shown below.

RSLT

Result

RSLT=0

Input voltage * PGA Gain < internal reference voltage

RSLT=1

Input voltage * PGA Gain > internal reference voltage

When the input voltage * PGA Gain is equal to the internal reference voltage, the level of bit RSLT is

undefined.

When CE pin set to 1, all of the MOSFETs are disable. Executing STCH command to enable the MOSFET accordingly.

Each of these MOSFETs could be enabled or disable individually.

M1_EN

M2_EN

M3_EN

M4_EN

MOSFET

0

0

0

0

All MOSFETs turn off

1

0

0

0

MOSFET 1 turn on

0

1

0

0

MOSFET 2 turn on

0

0

1

0

MOSFET 3 turn on

0

0

0

1

MOSFET 4 turn on

1

1

1

1

All MOSFETs turn on