P8/29

Rev. M, May 2010

ML5012

1-1.

WR_STCH Command. Select PGA input channel (CHAB_SEL & CHB_SEL), enable oscillator (ENOSC) for A/D,

AD Range Selection (AD_Range) and MOSFET Enable control (M1_EN, M2_EN, M3_EN & M4_EN).

The following diagram shows the timing of sending WR_STCH command.

The DIN data in C1~C4 cycle is WR_STCH command code.

The DIN data in C5 cycle is Oscillator Enable bit, D11 = ENOSC.

The DIN data in C6 cycle is AD Range Selection bit, D10 = AD_Range

The DIN data in C7~C9 cycle is Channel AB selection, D[9:7] = CHAB_SEL[2:0].

The DIN data in C10~C12 cycle is Channel B selection, D[6:4] = CHB_SEL[2:0].

The DIN data in C13 cycle is MOSFET 1 Enable, D3= M1_EN.

The DIN data in C14 cycle is MOSFET 2 Enable, D2= M2_EN.

The DIN data in C15 cycle is MOSFET 3 Enable, D1= M3_EN.

The DIN data in C16 cycle is MOSFET 4 Enable, D0= M4_EN.