Features

eroflex Circuit Technology – MIPS RISC Microprocessors © SCD7000SC REV B 7/30/01

Pad Buffer

Address Buffer

BLOCK DIAGRAM

instruction prefetch optimized for system level

price/performance

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150, 200, 210, 225 MHz operating frequency

Consult Factory for latest speeds

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MIPS IV Superset Instruction Set Architecture

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600 MB per second peak throughput

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75 MHz max. freq., multiplexed address/data

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Supports 1/2 clock multipliers (2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9)

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IEEE 1149.1 JTAG (TAP) boundary scan

associative with 32 byte line size

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16KB instruction

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16KB data: non-blocking and write-back or write-through

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256KB on-chip secondary: unified, non-blocking, block writeback

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Data PREFETCH instruction allows the processor to overlap cache

miss latency and instruction execution

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Floating point combined multiply-add instruction increases

performance in signal processing and graphics applications

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Conditional moves reduce branch frequency

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Index address modes (register + register)

filter components

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Fully associative joint TLB (shared by I and D translations)

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48 dual entries map 96 pages

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4 entry DTLB and 4 entry ITLB

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Variable page size (4KB to 16MB in 4x increments)

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Specialized DSP integer Multiply-Accumulate instruction,

(MAD/MADU) and three-operand multiply instruction (MUL/U)

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Per line cache locking in primaries and secondary

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Bypass secondary cache option

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I&D Test/Break-point (Watch) registers for emulation & debug

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Performance counter for system and software tuning & debug

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Ten fully prioritized vectored interrupts - 6 external, 2 internal, 2

software

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Fast Hit-Writeback-Invalidate and Hit-Invalidate cache operations

for efficient cache management

maximum

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Single cycle repeat rate for common single-precision operations

and some double-precision operations

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Single cycle repeat rate for single-precision combined multiply-

add operations

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Two cycle repeat rate for double-precision multiply and

double-precision combined multiply-add operations

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Standby reduced power mode with WAIT instruction

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4 watts typical @ 2.5V Int., 3.3V I/O, 200MHz

rotation as the commercial QED RM5261

64-Bit Superscaler Microprocessor

ACT 7000SC

A/D Bus

Pad Bus

M-Pipe Bus

DVA

D Bus

F-Pipe Bus

ITag

DTLB

DTag

ITLB

Set B

Secondary Tags

Set A

Secondary Tags

Set C

Secondary Tags

Set D

Secondary Tags

4 - Way Set Associative

Primary Data Cache

On - Chip 256K Byte Secondary Cache, 4 - Way Set Associative

4 - Way Set Associative

Primary Instruction Cache

Store Buffer

Write Buffer

Read Buffer

Prefetch Buffer

Instruction Dispatch Unit

M Pipe Register

F Pipe Register

Floating-Point

Load / Align

Floating-Point

Register File

Packer / Unpacker

Comparator

Floating-Point

MultAdd, Add, Sub,

Cvt, Div, Sqrt

Multiplier Array

IVA

Program Counter

ITLB Virtuals

Branch PC Adder

PC Incrementer

System / Memory

Control

Joint TLB

Coprocessor 0

Int Mult. Div. Madd

PLL/Clocks

FA Bus

Load Aligner

Integer Register File

M Pipe

F Pipe

DTLB Virtuals

Adder

StAin/Sh

Shifter

Adder

Logicals

Logicals