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Data Sheet

AD9763/AD9765/AD9767

Rev. G | Page 25 of 44

Interleaved Mode Timing

When the MODE pin is at Logic 0, the AD9763/AD9765/AD9767

operate in interleaved mode (refer to Figure 61). In addition,

WRT1 functions as IQWRT, CLK1 functions as IQCLK, WRT2

functions as IQSEL, and CLK2 functions as IQRESET.

Data enters the device on the rising edge of IQWRT. The logic level

of IQSEL steers the data to either Channel Latch 1 (IQSEL = 1) or

to Channel Latch 2 (IQSEL = 0). For proper operation, IQSEL

must change state only when IQWRT and IQCLK are low.

When IQRESET is high, IQCLK is disabled. When IQRESET

goes low, the next rising edge on IQCLK updates both DAC

latches with the data present at their inputs. In the interleaved

mode, IQCLK is divided by 2 internally. Following this first

rising edge, the DAC latches are only updated on every other

rising edge of IQCLK. In this way, IQRESET can be used to

synchronize the routing of the data to the DACs.

Similar to the order of CLK and WRT in dual-port mode,

IQCLK must occur before or simultaneously with IQWRT.

Timing specifications for interleaved mode are shown in Figure 64

and Figure 66.

The digital inputs are CMOS compatible with logic thresholds,

VTHRESHOLD, set to approximately half the digital positive supply

(DVDDx), or

VTHRESHOLD = DVDDx/2(±20%)

DATA IN

IQSEL

IQWRT

IQCLK

IOUTA

IOUTB

*APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY.

500 ps

tPD

tLPW

tH*

Figure 64. 5 V or 3.3 V Interleaved Mode Timing

At 5 V it is permissible to drive IQWRT and IQCLK together as

shown in Figure 65, but at 3.3 V the interleaved data transfer is

not reliable.

DATA IN

IQSEL

IQWRT

IQCLK

IOUTA

IOUTB

*APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY.

tH*

tPD

tLPW

Figure 65. 5 V Only Interleaved Mode Timing

IQSEL

IQWRT

IQCLK

IQRESET

INTERLEAVED

DATA

DAC OUTPUT

PORT 1

DAC OUTPUT

PORT 2

Figure 66. Interleaved Mode Timing

The internal digital circuitry of the AD9763/AD9765/AD9767

is capable of operating at a digital supply of 3.3 V or 5 V. As a

result, the digital inputs can also accommodate TTL levels when

DVDD1/DVDD2 is set to accommodate the maximum high

level voltage (VOH(MAX)) of the TTL drivers. A DVDD1/DVDD2

of 3.3 V typically ensures proper compatibility with bipolar TTL

logic families. Figure 67 shows the equivalent digital input

circuit for the data and clock inputs. The sleep mode input is

similar, with the exception that it contains an active pull-down

circuit, thus ensuring that the AD9763/AD9765/AD9767

remains enabled if this input is left disconnected.

DIGITAL

INPUT

DVDD1

Figure 67. Equivalent Digital Input

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