MC68331TS datasheet(59/84 Pages) FREESCALE

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MC68331TS/D

MSTR — Master/Slave Mode Select

0 = QSPI is a slave device and only responds to externally generated serial data.

1 = QSPI is system master and can initiate transmission to external SPI devices.

MSTR configures the QSPI for either master or slave mode operation. This bit is cleared on reset and

may only be written by the CPU.

WOMQ — Wired-OR Mode for QSPI Pins

0 = Outputs have normal MOS drivers.

1 = Pins designated for output by DDRQS have open-drain drivers.

WOMQ allows the wired-OR function to be used on QSPI pins, regardless of whether they are used as

general-purpose outputs or as QSPI outputs. WOMQ affects the QSPI pins regardless of whether the

QSPI is enabled or disabled.

BITS — Bits Per Transfer

In master mode, when BITSE in a command is set, the BITS field determines the number of data bits

transferred. When BITSE is cleared, eight bits are transferred. Reserved values default to eight bits.

BITSE is not used in slave mode.

The following table shows the number of bits per transfer.

CPOL — Clock Polarity

0 = The inactive state value of SCK is logic level zero.

1 = The inactive state value of SCK is logic level one.

CPOL is used to determine the inactive state value of the serial clock (SCK). It is used with CPHA to

produce a desired clock/data relationship between master and slave devices.

CPHA — Clock Phase

0 = Data is captured on the leading edge of SCK and changed on the following edge of SCK.

1 = Data is changed on the leading edge of SCK and captured on the following edge of SCK.

CPHA determines which edge of SCK causes data to change and which edge causes data to be cap-

tured. CPHA is used with CPOL to produce a desired clock/data relationship between master and slave

devices. CPHA is set at reset.

BITS

Bits per Transfer

0000

0001

Reserved

0010

Reserved

0011

Reserved

0100

Reserved

0101

Reserved

0110

Reserved

0111

Reserved

1000

1001

1010

1011

1100

1101

1110

1111

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