MC68331TS datasheet(20/84 Pages) FREESCALE

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MC68331TS/D

3.2.5 Spurious Interrupt Monitor

The spurious interrupt monitor issues BERR if no interrupt arbitration occurs during an interrupt-ac-

knowledge cycle.

3.2.6 Software Watchdog

The software watchdog is controlled by SWE in the SYPCR. Once enabled, the watchdog requires that

a service sequence be written to SWSR on a periodic basis. If servicing does not take place, the watch-

dog times out and issues a reset. This register can be written at any time, but returns zeros when read.

Perform a software watchdog service sequence as follows:

Write $55 to SWSR.

Write $AA to SWSR.

Both writes must occur before time-out in the order listed, but any number of instructions can be exe-

cuted between the two writes.

The watchdog clock rate is affected by SWP and SWT in SYPCR. When SWT[1:0] are modified, a

watchdog service sequence must be performed before the new time-out period takes effect.

The reset value of SWP is affected by the state of the MODCLK pin on the rising edge of reset, as shown

in the following table.

3.2.7 Periodic Interrupt Timer

The periodic interrupt timer (PIT) generates interrupts of specified priorities at specified intervals. Timing

for the PIT is provided by a programmable prescaler driven by the system clock.

This register contains information concerning periodic interrupt priority and vectoring. Bits [10:0] can be

read or written at any time. Bits [15:11] are unimplemented and always return zero.

PIRQL[2:0] —Periodic Interrupt Request Level

The following table shows what interrupt request level is asserted when a periodic interrupt is generat-

ed. If a PIT interrupt and an external IRQ signal of the same priority occur simultaneously, the PIT in-

terrupt is serviced first. The periodic timer continues to run when the interrupt is disabled.

SWSR —Software Service Register

$YFFA27

NOT USED

RESET:

MODCLK

SWP

PICR — Periodic Interrupt Control Register

$YFFA22

PIRQL

PIV

RESET:

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