MOTOROLA

MPC565/MPC566 Product Brief

5

Detailed Feature List

1.2.10 Debug Features

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Extensive system debug support

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On-chip watchpoints and breakpoints

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Program flow tracking

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Background debug mode (BDM)

1.2.10.1 Nexus Debug Port (Class 3)

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Nexus/IEEE – ISTO 5001-1999 debug port (Class 3)

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Nine- or 16-pin interface

1.2.10.2 Message Data Link Controller (DLCMD2) Module

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Two pins muxed with QSMCMB pins. Muxing controlled by QSMCMB PCS3 pin assignment

register

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SAE J1850 Class B data communications network interface compatible and ISO compatible for

low-speed (

<125 Kbps) serial data communications in automotive applications

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10.4 Kbps variable pulse width (VPW) bit format

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Digital noise filter, collision detection

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Hardware cyclical redundancy check (CRC) generation and checking

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Block mode receive and transmit supported

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4x receive mode supported (41.6 Kbps)

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Digital loopback mode

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In-frame response (IFR) types 0, 1, 2, and 3 supported

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Dedicated register for symbol timing adjustments

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Inter-module bus 3 (IMB3) slave interface

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Power-saving IMB3 stop mode with automatic wakeup on network activity

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Power-saving IMB3 CLOCKDIS mode

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Debug mode available through IMB3 FREEZE signal or user controllable SOFT_FRZ bit

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Polling and IMB3 interrupt generation with vector lookup available

1.2.11 Integrated I/O System

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True 5-V I/O

1.2.11.1 Time Processor Units (TPU3)

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Three time processing units (TPU3)

— 16 channels each

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Each TPU3 is a microcoded timer subsystem

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One 6-Kbyte and one 4-Kbyte dual-port TPU RAM (DPTRAM), one (6-Kbyte) shared by two

TPU3 modules for TPU microcode and the 4-Kbyte dedicated to the third TPU3 for microcode.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com