AD7960BCPZ datasheet(14/24 Pages) AD

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AD7960

Data Sheet

Rev. 0 | Page 14 of 24

THEORY OF OPERATION

Figure 28. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7960 is a 5 MSPS, high precision, power efficient, 18-bit

ADC that uses SAR-based architecture to provide performance

of 99 dB SNR, ±0.8 LSB INL, and ±0.5 LSB DNL. The AD7960

does not exhibit any pipeline delay or latency, making it ideal

for multiplexed channel applications.

The AD7960 is capable of converting 5,000,000 samples per

second (5 MSPS). The device typically consumes 46.5 mW of

power. The AD7960 offers the added functionality of an on-

chip reference buffer. If the internal reference buffer is enabled,

the AD7960 consumes approximately an additional 18 mW of

power.

The AD7960 is specified for use with 5 V and 1.8 V supplies

(VDD1, VDD2). The interface from the digital host to the

AD7960 uses 1.8 V logic only. The AD7960 uses an LVDS

interface to transfer data conversions. The CNV+ and CNV−

inputs to the part activate the conversion of the analog input.

The CNV+ and CNV− pins can be applied using a CMOS or

LVDS source.

The AD7960 is housed in a space-saving, 32-lead, 5 mm ×

5 mm LFCSP package.

CONVERTER INFORMATION

The AD7960 is a 5 MSPS ADC that uses SAR-based archi-

tecture based on a charge redistribution DAC. Figure 28 shows

a simplified schematic of the ADC. The capacitive DAC consists

of two identical arrays of 18 binary weighted capacitors that are

connected to the two comparator inputs.

During the acquisition phase, the terminals of the array tied

to the input of the comparator are connected to GND via SW+

and SW−. All independent switches are connected to the analog

inputs. In this way, the capacitor arrays are used as sampling

capacitors and acquire the analog signal on the IN+ and IN−

inputs. A conversion phase is initiated when the acquisition

phase is complete and the CNV± input goes high. Note that the

AD7960 can receive a CMOS or LVDS format CNV± signal.

When the conversion phase begins, SW+ and SW− are opened

first. The two-capacitor arrays are then disconnected from the

inputs and connected to the GND input. Therefore, the differential

voltage between the inputs (IN+ and IN−) captured at the end

of the acquisition phase is applied to the comparator inputs,

causing the comparator to become unbalanced. By switching

each element of the capacitor array between GND and REF (the

reference voltage), the comparator input varies by binary

weighted voltage steps (VREF/2, VREF/4 … VREF/262,144). The

control logic toggles these switches, MSB first, to bring the

comparator back into a balanced condition. At the completion

of this process, the control logic generates the ADC output code.

The AD7960 digital interface uses low voltage differential

signaling (LVDS) to enable high data transfer rates.

The AD7960 conversion result is available for reading after

tMSB (time from the conversion start until MSB is available)

elapses. The user must apply a burst LVDS CLK± signal to the

AD7960 to transfer data to the digital host.

The CLK± signal outputs the ADC conversion result onto the

data output, D±. The bursting of the CLK± signal, illustrated in

Figure 35 and Figure 36, is characterized as follows:

•

Hold the differential voltage on CLK± in a steady state in

the window of time between tCLKL and tMSB.

•

The AD7960 has two data read modes. For more

information about the echoed clock and self clocked

interface modes, see the Digital Interface section.

SW+

COMP

SW–

IN+

REF

GND

LSB

MSB

131,072C

65,536C

CNV+, CNV–

IN–

131,072C

65,536C

LSB

MSB

GND

LVDS INTERFACE

OUTPUT CODE

SWITCHES

CONTROL

CLK+, CLK–

DCO+, DCO–

D+, D–

DATA

TRANSFER

CONVERSION

CONTROL

LOGIC

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