Data Sheet

AD7960

Rev. 0 | Page 21 of 24

Figure 37. Self Clocked Interface Mode with Extra Clock Pulse Timing Diagram

CLK+

20

19

21

1

4

2

1

2

3

D+

D–

CLK–

D0

N – 1

D1

N – 1

ACQUISITION

ACQUISITION

20

21

19

3

D17

N

D16

N

D1

N

0

0

1

D0

N

D17

N + 1

0

0

1

CNV+

SAMPLE N

SAMPLE N + 1

CNV–

ACQUISITION