STM32L151VBT6DTR datasheet(18/121 Pages) STMICROELECTRONICS

18 / 121 page

Functional overview

STM32L151x6/8/B, STM32L152x6/8/B

18/121

Doc ID 17659 Rev 8

Nested vectored interrupt controller (NVIC)

The ultra-low-power STM32L15xxx embeds a nested vectored interrupt controller able to

handle up to 45 maskable interrupt channels (not including the 16 interrupt lines of

Cortex™-M3) and 16 priority levels.

●

Closely coupled NVIC gives low-latency interrupt processing

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Interrupt entry vector table address passed directly to the core

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Closely coupled NVIC core interface

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Allows early processing of interrupts

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Processing of late arriving, higher-priority interrupts

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Support for tail-chaining

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Processor state automatically saved

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Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

3.3

Reset and supply management

3.3.1

Power supply schemes

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VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator.

Provided externally through VDD pins.

●

VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs

and PLL (minimum voltage to be applied to VDDA is 1.8 V when the ADC is used).

VDDA and VSSA must be connected to VDD and VSS, respectively.

3.3.2

Power supply supervisor

The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset

(PDR) that can be coupled with a brownout reset (BOR) circuitry.

The device exists in two versions:

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The version with BOR activated at power-on operates between 1.8 V and 3.6 V.

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The other version without BOR operates between 1.65 V and 3.6 V.

After the VDD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or

not at power-on), the option byte loading process starts, either to confirm or modify default

thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes

1.65 V (whatever the version, BOR active or not, at power-on).

When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever

the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the

power ramp-up should guarantee that 1.65 V is reached on VDD at least 1 ms after it exits

the POR area.

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