AD5258BRMZ100-R7 datasheet(5/24 Pages) AD

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Data Sheet

AD5258

Rev. D | Page 5 of 24

TIMING CHARACTERISTICS

VDD = VLOGIC = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +85°C, unless otherwise noted.

Table 2.

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

I2C INTERFACE TIMING CHARACTERISTICS

SCL Clock Frequency

fSCL

400

kHz

tBUF Bus-Free Time Between Stop and Start

1.3

µs

tHD;STA Hold Time (Repeated start)

After this period, the first clock pulse is

generated.

0.6

µs

tLOW Low Period of SCL Clock

1.3

µs

tHIGH High Period of SCL Clock

0.6

µs

tSU;STA Setup Time for Repeated Start Condition

0.6

µs

tHD;DAT Data Hold Time

0.9

µs

tSU;DAT Data Setup Time

100

tF Fall Time of Both SDA and SCL Signals

300

tR Rise Time of Both SDA and SCL Signals

300

tSU;STO Setup Time for Stop Condition

t10

0.6

µs

EEPROM Data Storing Time

tEEMEM_STORE

EEPROM Data Restoring Time at Power On1

tEEMEM_RESTORE1

VDD rise time dependant. Measure with-

out decoupling capacitors at VDD and GND.

300

µs

EEPROM Data Restoring Time upon Restore

Command1

tEEMEM_RESTORE2

VDD = 5 V.

300

µs

EEPROM Data Rewritable Time2

tEEMEM_REWRITE

540

µs

FLASH/EE MEMORY RELIABILITY

Endurance3

100

700

kCycles

Data Retention4

100

Years

During power-up, the output is momentarily preset to midscale before restoring EEPROM content.

Delay time after power-on preset prior to writing new EEPROM data.

Endurance is qualified to 100,000 cycles per JEDEC Std. 22 Method A117 and is measured at −40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.

Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates

with junction temperature.

SCL

SDA

t10

Figure 3. I2C Interface Timing Diagram

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