AD9974BBCZ datasheet(16/52 Pages) AD

部品番号	AD9974BBCZ

部品情報	Dual-Channel, 14-Bit, CCD Signal Processor with Precision Timing Core

PDF	52 Pages

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メーカー	AD [Analog Devices]

ホームページ	http://www.analog.com

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16 / 52 page

AD9974

Rev. A | Page 16 of 52

H1 TO H4 PROGRAMMABLE LOCATIONS:

1H1 RISING EDGE.

2H1 FALLING EDGE.

3H2 RISING EDGE.

4H2 FALLING EDGE.

H2, H4

H1, H3

Figure 19. HCLK Mode 2 Operation

H1 TO H4 PROGRAMMABLE LOCATIONS:

1H1 RISING EDGE.

2H1 FALLING EDGE.

3H3 RISING EDGE.

4H3 FALLING EDGE.

Figure 20. HCLK Mode 3 Operation

NOTES

1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN ONE PIXEL PERIOD.

TYPICAL POSITIONS FOR EACH SIGNAL ARE SHOWN. HCLK MODE 1 IS SHOWN.

2. CERTAIN POSITIONS SHOULD BE AVOIDED FOR EACH SIGNAL, SHOWN ABOVE AS INHIBIT REGIONS.

3. IF A SETTING IN THE INHIBIT REGION IS USED, AN UNSTABLE PIXEL SHIFT CAN OCCUR IN THE HBLK LOCATION OR AFE PIPELINE.

P[0]

CLI

P[64] = P[0]

CCD

SIGNAL

P[32]

P[16]

P[48]

POSITION

RGr[0]

RGf[16]

SHD

SHDLOC[0]

H1r[0]

H1f[32]

tS1

SHP

SHPLOC[32]

DOUTPHASEP

DATAPHASEP[32]

tDOUTINH

tSHDINH

tSHPINH

Figure 21. High Speed Timing Default Locations

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