ADuC7023BCPZ62I-R7 datasheet(79/96 Pages) AD

部品番号	ADuC7023BCPZ62I-R7

部品情報	Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU with Enhanced IRQ Handler

PDF	96 Pages

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メーカー	AD [Analog Devices]

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79 / 96 page

Data Sheet

ADuC7023

| Page 79 of 96

IRQVEC Register

The IRQ interrupt vector register, IRQVEC, points to a memory

address containing a pointer to the interrupt service routine of

the currently active IRQ. This register should only be read when

an IRQ occurs and IRQ interrupt nesting has been enabled by

setting Bit 0 of the IRQCONN register.

IRQVEC Register

Name:

IRQVEC

Address:

0xFFFF001C

Default value: 0x00000000

Access:

Read only

Table 91. IRQVEC MMR Bit Designations

Bit

Type

Initial

Value

Description

31 to 23

Read only

Always read as 0.

22 to 7

R/W

IRQBASE register value.

6 to 2

Read only

Highest priority source. This is

a value between 0 and 21

representing the possible

interrupt sources. For example,

if the highest currently active

IRQ is Timer 2, then these bits

are [00100].

1 to 0

Reserved

Reserved bits.

Priority Registers

The IRQ interrupt vector register, IRQVEC, points to a memory

address containing a pointer to the interrupt service routine of

the currently active IRQ. This register should only be read when

an IRQ occurs and IRQ interrupt nesting has been enabled by

setting Bit 0 of the IRQCONN register.

Rev. E

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