MPC8548ECPXATJB datasheet(3/151 Pages) FREESCALE

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9

Freescale Semiconductor

Overview

— Performance monitor facility that is similar to, but separate from, the device performance

monitor

The e500 defines features that are not implemented on this device. It also generally defines some features

that this device implements more specifically. An understanding of these differences can be critical to

ensure proper operations.

•

512-Kbyte L2 cache/SRAM

— Flexible configuration.

— Full ECC support on 64-bit boundary in both cache and SRAM modes

— Cache mode supports instruction caching, data caching, or both.

— External masters can force data to be allocated into the cache through programmed memory

ranges or special transaction types (stashing).

— 1, 2, or 4 ways can be configured for stashing only.

— Eight-way set-associative cache organization (32-byte cache lines)

— Supports locking entire cache or selected lines. Individual line locks are set and cleared through

Book E instructions or by externally mastered transactions.

— Global locking and Flash clearing done through writes to L2 configuration registers

— Instruction and data locks can be Flash cleared separately.

— SRAM features include the following:

– I/O devices access SRAM regions by marking transactions as snoopable (global).

– Regions can reside at any aligned location in the memory map.

– Byte-accessible ECC is protected using read-modify-write transaction accesses for

smaller-than-cache-line accesses.

•

Address translation and mapping unit (ATMU)

— Eight local access windows define mapping within local 36-bit address space.

— Inbound and outbound ATMUs map to larger external address spaces.

– Three inbound windows plus a configuration window on PCI/PCI-X and PCI Express

– Four inbound windows plus a default window on RapidIO™

– Four outbound windows plus default translation for PCI/PCI-X and PCI Express

– Eight outbound windows plus default translation for RapidIO with segmentation and

sub-segmentation support

•

DDR/DDR2 memory controller

— Programmable timing supporting DDR and DDR2 SDRAM

— 64-bit data interface

— Four banks of memory supported, each up to 4 Gbytes, to a maximum of 16 Gbytes

— DRAM chip configurations from 64 Mbits to 4 Gbits with ×8/×16 data ports

— Full ECC support

— Page mode support

– Up to 16 simultaneous open pages for DDR

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