MPC8548ECPXATJB datasheet(13/151 Pages) FREESCALE

13 / 151 page

MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9

Freescale Semiconductor

Electrical Characteristics

2.1.3

Output Driver Characteristics

The following table provides information on the characteristics of the output driver strengths. The values

are preliminary estimates.

2.2

Power Sequencing

The device requires its power rails to be applied in a specific sequence in order to ensure proper device

operation. These requirements are as follows for power-up:

1. VDD, AVDD_n, BVDD, LVDD, OVDD, SVDD, TVDD, XVDD

2. GVDD

All supplies must be at their stable values within 50 ms.

NOTE

Items on the same line have no ordering requirement with respect to one

another. Items on separate lines must be ordered sequentially such that

voltage rails on a previous step must reach 90% of their value before the

voltage rails on the current step reach 10% of theirs.

NOTE

In order to guarantee MCKE low during power-up, the above sequencing for

GVDD is required. If there is no concern about any of the DDR signals being

in an indeterminate state during power-up, then the sequencing for GVDD is

not required.

Table 3. Output Drive Capability

Driver Type

Programmable

Output Impedance

(

)

Supply

Voltage

Notes

Local bus interface utilities signals

BVDD = 3.3 V

BVDD = 2.5 V

45(default)

BVDD = 3.3 V

BVDD = 2.5 V

PCI signals

OVDD = 3.3 V

45(default)

DDR signal

36 (half strength mode)

GVDD = 2.5 V

DDR2 signal

36 (half strength mode)

GVDD = 1.8 V

TSEC/10/100 signals

L/TVDD = 2.5/3.3 V

—

DUART, system control, JTAG

OVDD = 3.3 V

—

I2C

150

OVDD = 3.3 V

—

Notes:

1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR.

2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT1 signal at reset.

3. The drive strength of the DDR interface in half-strength mode is at Tj = 105C and at GVDD (min).

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