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TS52002

Version 1.2

Specifications subject to change

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Copyright © 2011, Triune Systems, LLC

REGISTER DESCRIPTION (Device Address = 0x48)

REGISTER

ADDRESS (HEX)

NAME

DESCRIPTION

0

00

STATUS

Status bit register

1-31

N/A

N/A

Registers not implemented

STATUS REGISTER (STATUS)

Address – 0x00h

DATA BIT

D7

D6

D5

D4

D3

D2

D1

D0

FIELD NAME

VBAT_OV

Not Used

Not Used

Not Used

TSD

Not Used

VIN_UV

Not Used

READ/WRITE

R

R

R

R

R

R

R

R

FIELD NAME

VBAT_OV

VBAT over-voltage

TSD

Thermal shutdown

VIN_UV

VIN under-voltage

(1) Faults are defined as VBAT_OV. Warnings are defined as TSD, and VIN_UV. Faults cause the nFLT pin to be pulled low,

Warnings do not cause the nFLT pin to be pulled low. All status bits are cleared after register read access. nFLT pin will go

high impedance (open drain output) after the status register has been read and all status bits have been reset.

CONFIGURATION REGISTER

Address – 0x04h

DATA BIT

D7

D6

D5

D4

D3

D2

D1

D0

FIELD NAME

MAX_CHRG_CURR [3:0]

Not Used

READ/WRITE

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

FIELD NAME

BIT DEFINITION

MAX_CHRG_CURR[3:0]

Maximum charge current configuration

0000 – 50 mA

0001 – 100 mA

0010 – 200 mA

0011 – 300 mA

0100 – 400 mA

0101 – 500 mA

0110 – 600 mA

0111 – 700 mA

1000 – 800 mA

1001 – 900 mA

1010 – 1000 mA

1011 – 1100 mA

1100 – 1200 mA

1101 – 1300 mA

1110 – 1400 mA

1111 – 1500 mA

EXTERNAL COMPONENT SELECTION

The internal compensation is optimized for a 4.7uF output capacitor and a 4.7uH inductor. To keep the output ripple low, a

low ESR (less than 35mOhm) ceramic is recommended.