AX2000 datasheet(64/262 Pages) MICROSEMI

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Detailed Specifications

2- 50

R e v i sio n 1 8

Differential Standards

Physical Implementation

Implementing differential I/O standards requires the configuration of a pair of external I/O pads, resulting

in a single internal signal. To facilitate construction of the differential pair, a single I/O Cluster contains the

resources for a pair of I/Os. Configuration of the I/O Cluster as a differential pair is handled by Designer

software when the user instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

support for bidirectional I/Os or tristates with these standards.

LVDS

Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It requires

that one data bit is carried through two signal lines, so two pins are needed. It also requires an external

resistor termination. The voltage swing between these two signal lines is approximately 350 mV.

The LVDS circuit consists of a differential driver connected to a terminated receiver through a constant-

impedance transmission line. The receiver is a wide-common-mode-range differential amplifier. The

common-mode range is from 0.2 V to 2.2 V for a differential input with 400 mV swing.

To implement the driver for the LVDS circuit, drivers from two adjacent I/O cells are used to generate the

differential signals (note that the driver is not a current-mode driver). This driver provides a nominal

constant current of 3.5 mA. When this current flows through a 100

Ω termination resistor on the receiver

side, a voltage swing of 350 mV is developed across the resistor. The direction of the current flow is

controlled by the data fed to the driver.

An external-resistor network (three resistors) is needed to reduce the voltage swing to about 350 mV.

Therefore, four external resistors are required, three for the driver and one for the receiver.

Figure 2-25 • LVDS Board-Level Implementation

140

100

ZO = 50

165

–

INBUF_LVDS

OUTBUF_LVDS

FPGA

Table 2-56 • DC Input and Output Levels

DC Parameter

Description

Min.

Typ.

Max.

Units

VCCI1

Supply Voltage

2.375

2.5

2.625

VOH

Output High Voltage

1.25

1.425

1.6

VOL

Output Low Voltage

0.9

1.075

1.25

VODIFF

Differential Output Voltage

250

350

450

VOCM

Output Common Mode Voltage

1.125

1.25

1.375

VICM2

Input Common Mode Voltage

0.2

1.25

2.2

Notes:

1. ±5%

2. Differential input voltage = ±350 mV.

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