CD00237391 datasheet(33/177 Pages) STMICROELECTRONICS

33 / 177 page

STM32F20xxx

Description

Doc ID 15818 Rev 9

33/177

2.2.33

GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain,

with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)

or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog

alternate functions. All GPIOs are high-current-capable and have speed selection to better

manage internal noise, power consumption and electromagnetic emission.

The I/O alternate function configuration can be locked if needed by following a specific

sequence in order to avoid spurious writing to the I/Os registers.

To provide fast I/O handling, the GPIOs are on the fast AHB1 bus with a clock up to

120 MHz that leads to a maximum I/O toggling speed of 60 MHz.

2.2.34

ADCs (analog-to-digital converters)

Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16

external channels, performing conversions in the single-shot or scan mode. In scan mode,

automatic conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

●

Simultaneous sample and hold

●

Interleaved sample and hold

The ADC can be served by the DMA controller. An analog watchdog feature allows very

precise monitoring of the converted voltage of one, some or all selected channels. An

interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the timers TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 can be

internally connected to the ADC start trigger and injection trigger, respectively, to allow the

application to synchronize A/D conversion and timers.

2.2.35

DAC (digital-to-analog converter)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two

analog voltage signal outputs. The design structure is composed of integrated resistor

strings and an amplifier in inverting configuration.

This dual digital Interface supports the following features:

●

two DAC converters: one for each output channel

●

8-bit or 12-bit monotonic output

●

left or right data alignment in 12-bit mode

●

synchronized update capability

●

noise-wave generation

●

triangular-wave generation

●

dual DAC channel independent or simultaneous conversions

●

DMA capability for each channel

●

external triggers for conversion

●

input voltage reference VREF+

Eight DAC trigger inputs are used in the device. The DAC channels are triggered through

the timer update outputs that are also connected to different DMA streams.

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