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STM8S103F2 データシート(PDF) 82 Page - STMicroelectronics |
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STM8S103F2 データシート(HTML) 82 Page - STMicroelectronics |
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82 / 117 page  Figure 38: Recommended reset pin protection External reset circuit (optional) 0.1 μF NRST VDD RPU Filter Internal reset STM8 SPI serial peripheral interface 10.3.8 Unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions. tMASTER = 1/fMASTER. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 43: SPI characteristics Unit Max Min Conditions (1) Parameter Symbol MHz 8 0 Master mode SPI clock frequency fSCK1/ tc(SCK) MHz 7 (2) 0 SPI clock frequency fSCK1/ tc(SCK) fSCK1/ tc(SCK) ns 25 - Capacitive load: C = 30 pF SPI clock rise and fall time tr(SCK) tf(SCK) - 4 x tMASTER Slave mode NSS setup time tsu(NSS) (3) - 70 Slave mode NSS hold time th(NSS) (3) tSCK/ 2 +15 tSCK/ 2 - 15 Master mode SCK high and low time tw(SCKH) (3) tw(SCKL) (3) - 5 Master mode Data input setup time tsu(MI) (3) tsu(SI) (3) - 5 Slave mode - 7 Master mode Data input hold time th(MI) (3) th(SI) (3) - 10 Slave mode DocID15441 Rev 9 82/117 STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics |
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