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TCS3404CS データシート(PDF) 20 Page - ams AG |
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TCS3404CS データシート(HTML) 20 Page - ams AG |
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20 / 41 page ![]() TCS3404, TCS3414 DIGITAL COLOR SENSORS TAOS137A − APRIL 2011 19 The LUMENOLOGY r Company r r Copyright E 2011, TAOS Inc. www.taosinc.com Gain Register (07h) The Gain register provides a common gain control adjustment for all four parallel ADC output channels. Two gain bits [5:4] in the Gain Register allow the relative gain to be adjusted from 1 × to 64× in 4× increments. The advantage of the gain adjust is to extend the dynamic range of the light input up to a factor of 64 × before analog or digital saturation occurs. If analog saturation has occurred, lowering the gain sensitivity will likely prevent analog saturation especially when the integration time is relatively short. For longer integration times, the 16-bit output could be in digital saturation (64K). If lowering the gain to 1 × does not prevent digital saturation from occurring, the use of PRESCALER can be useful. The PRESCALER is 3 bits [2:0] in the gain register that divides down the output count (i.e. shifts the LSB of the count value to the right). The PRESCALER adjustment range is divide by 1 to 64 in multiples of 2. The most sensitive gain setting of the device would be when GAIN is set to 11b (64 ×), and PRESCALER is set to 000b (divide by 1). The least sensitive part setting would be GAIN 00 (1 ×) and PRESCALER 110 (divide by 64). If the part continues to be in digital saturation at the least sensitive setting, the integration time can be lowered (see Timing Register section). Table 9. Gain Register 6 75 4 2 31 0 0 00 0 0 00 0 Reset Value: GAIN Resv GAIN Resv 07h PRESCALER Resv FIELD BITS DESCRIPTION Resv 7:6 Reserved. Write as 0. Analog Gain Control. This field switches the common analog gain of the four ADC channels. Four gain modes are provided: FIELD VALUE GAIN GAIN 5:4 00 1 × GAIN 5:4 01 4 × 10 16 × 11 64 × Resv 3 Reserved. Write as 0. Prescaler. This field controls a 6-bit digital prescaler and divider. The prescaler reduces the sensitivity of each ADC integrator as shown in the table below: FIELD VALUE PRESCALER MODE 000 Divide by 1. 001 Divide by 2. PRESCALER 2:0 010 Divide by 4. PRESCALER 2:0 011 Divide by 8. 100 Divide by 16. 101 Divide by 32. 110 Divide by 64. 111 Not used. |
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