CS4812 datasheet(19/36 Pages) CIRRUS

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CS4812

DS291PP3

3.4

Clock Generation

The CS4812 master clock may be generated by us-

ing the on-chip oscillator with an external crystal or

may be derived from an external clock source.

3.4.1

Clock Source

The CS4812 requires a 256 Fs master clock to run

the internal logic. The two possible clock sources

are the on-chip crystal oscillator or an external clock

input to the XTI pin.

When using the on-chip crystal oscillator, external

loading capacitors are required. (see Figure 5) High

frequency crystals (>8 MHz) should be parallel

resonant, fundamental mode and designed for

20 pF loading. (equivalent to 40 pF to ground on

each leg)

3.5

Serial Control Port

The serial control port contains all of the main con-

trol logic for the chip. It controls power-on se-

quencing,

hardware

configuration

and

DSP

operation. In AutoBoot mode, the serial control

port manages the entire boot process including ini-

tialization of its own hardware configuration regis-

ters from EEPROM, code download from the

EEPROM to the DSP and initialization of the CO-

DEC. In host-controlled mode, the host-device ini-

tializes the hardware configuration registers and

downloads the application code to the DSP via 2

dedicated control port registers. Application mes-

saging between the host and the DSP is also done

via these control port registers. The operation of the

control port may be completely asynchronous to

the audio sample rate. However, it is recommended

that the control port pins remain static when not in

use.

The required control port register settings are con-

tained in the Crystal effects firmware application

code EEPROM image.

The control port supports the SPI bus and the I2C®

bus in both master and slave modes. The bus inter-

face is selected via the SPI/I2C pin and the mas-

ter/slave mode is selected via the SCPM/S pin.

These pins are sampled during de-assertion of the

RST pin.

Master mode is selected for stand-alone operation

when AutoBooting from an external serial EE-

PROM. Slave mode is selected when the CS4812 is

connected to an external host controller.

3.5.1

SPI Bus

The SPI bus interface consists of 5 digital signals,

CCLK, CDIN, CDOUT, CS and REQ. CCLK, the

control port bit clock, is used to clock individual data

bits. CDIN, the control data input, is the serial data

input line to the CS4812. CDOUT, the control data

output, is the output data line from the CS4812. It is

open-drain and requires a 2.2 k

Ω pull-up resistor.

CS, the chip select signal, is asserted low to enable

the SPI port. REQ, the request pin, is used by the

DSP to request a read by a host controller when op-

erating in control port slave mode. Data is clocked

into the chip on the rising edge of CCLK and out on

the falling edge. When in slave mode, the CLK sig-

nal must be synchronous with the internal DSP

clock. An external D flip flop off of CLKOUT as

shown in Figure 9 can be used to retime the CLK sig-

nal. There is limited drive capability on CLKOUT so

Line Out

From

CS4812

PIO

MMBT3906

MMBT3904

MMBT3906

10 k

Ω

10 k

Ω

10 k

Ω

GND

3.3 k

Ω

µF

1 k

Ω

µF

From Op-Amp

Figure 13. Output Mute Circuit

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