CS49400 datasheet(63/100 Pages) CIRRUS

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6.3.6 Motorola Parallel Host

Communication Mode for DSPC

The Motorola parallel host communication mode is

implemented using the pins given in Table 10.

Parallel host communication is available only on

the 144-pin package part. The INTREQ pin is

asserted (driven low) whenever the DSP has an

outgoing message for the host. This same

information is reflected by the HOUTRDY bit of

the Host Control Register (A[1:0] = 01b).

INTREQ is useful for informing the host of

unsolicited messages. An unsolicited message is

defined as a message generated by DSPC without

an associated host read request.

6.3.6.1 Writing a Byte in Motorola Mode for

DSPC

Information provided in this section is intended as

a functional description of how to write control

information to DSPC. The system designer must

ensure that all of the timing constraints of the

Motorola Parallel Host Mode Write Cycle are met.

The flow diagram shown in Figure 46 illustrates

the sequence of events that define a one-byte write

in Motorola mode. One byte writes should only be

used with the Host Control and Host Data registers.

The protocol presented in Figure 46 will now be

described in detail.

1) The host must first drive the A1 and A0 register

address pins of DSPC with the address of the

desired Parallel I/O Register. The address is

latched on the falling edge of CS.

Host Control:

A[1:0]==01b.

Host Data1:

A[1:0]==10b.

Host Data2:

A[1:0]==11b.

2) The host indicates that this is a write cycle by

driving the R/W pin low.

Mnemonic

Pin Name

144-Pin

Package,

Number

Chip Select

129

Data Strobe

120

Read or Write Select

R/W

121

139

130

Interrupt Request

INTREQ

Host Busy

HINBSY

141

DATA7

HDAT7

DATA6

HDAT6

DATA5

HDAT5

DATA4

HDAT4

103

DATA3

HDAT3

105

DATA2

HDAT2

112

DATA1

HDAT1

115

DATA0

HDAT0

116

Table 10. Motorola Mode Communication Signals for

DSPC

CS (HIGH)

DS (HIGH)

W RITE BYTE TO

HDAT[7:0]

CS (LOW )

DS (LOW )

R/W (LOW )

ADDRESS A PARALLEL I/O REGISTER

(A[1:0] SET APPROPRIATELY)

Figure 46. Motorola Mode, One-Byte Write Flow

Diagram for DSPC

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