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CS49400 データシート(PDF) 4 Page - Cirrus Logic

部品番号 CS49400
部品情報  Multi-Standard Audio Decoder Family
PDF  100 Pages
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メーカー  CIRRUS [Cirrus Logic]
ホームページ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS49400 データシート(HTML) 4 Page - Cirrus Logic

  CS49400 Datasheet HTML 1Page - Cirrus Logic CS49400 Datasheet HTML 2Page - Cirrus Logic CS49400 Datasheet HTML 3Page - Cirrus Logic CS49400 Datasheet HTML 4Page - Cirrus Logic CS49400 Datasheet HTML 5Page - Cirrus Logic CS49400 Datasheet HTML 6Page - Cirrus Logic CS49400 Datasheet HTML 7Page - Cirrus Logic CS49400 Datasheet HTML 8Page - Cirrus Logic CS49400 Datasheet HTML 9Page - Cirrus Logic Next Button
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LIST OF FIGURES
Figure 1. RESET Timing ..................................................................................................................... 9
Figure 2. CLKIN with CLKSEL = VSS = PLL Enable ........................................................................ 10
Figure 3. Intel® Parallel Host Mode Slave Read Cycle for DSPAB .................................................. 12
Figure 4. Intel® Parallel Host Mode Slave Write Cycle for DSPAB ................................................... 12
Figure 5. Intel® Parallel Host Slave Mode Read Cycle for DSPC ..................................................... 14
Figure 6. Intel® Parallel Host Slave Mode Write Cycle for DSPC ..................................................... 14
Figure 7. Motorola® Parallel Host Slave Mode Read Cycle for DSPAB ........................................... 16
Figure 8. Motorola® Parallel Host Slave Mode Write Cycle for DSPAB ........................................... 16
Figure 9. Motorola® Parallel Host Slave Mode Read Cycle for DSPC ............................................. 18
Figure 10. Motorola® Parallel Host Slave Mode Write Cycle for DSPC ............................................ 18
Figure 11. SPI Control Port Slave Mode Timing (DSPAB) ............................................................... 20
Figure 12. SPI Control Port Slave Mode Timing (DSPC) ................................................................. 22
Figure 13. Digital Audio Input Data, Slave Clock Timing .................................................................. 23
Figure 14. Serial Audio Input Data, Slave Clock Timing ................................................................... 24
Figure 15. Serial Compressed Data Timing ...................................................................................... 25
Figure 16. Parallel Data Timing ........................................................................................................ 26
Figure 17. Digital Audio Output Data, Input and Output Clock Timing ............................................. 28
Figure 18. Digital Audio Output Data, Input and Output Clock Timing ............................................. 28
Figure 19. SRAM/Flash Controller Timing Diagram - Write Cycle .................................................... 29
Figure 20. SRAM/Flash Controller Timing Diagram - Read Cycle .................................................... 29
Figure 21. SRAM/Flash Controller Timing Diagram - Single Byte Write Cycle ................................. 30
Figure 22. SRAM/Flash Controller Timing Diagram - Single Byte Read Cycle ................................ 30
Figure 23. SDRAM Controller Timing Diagram - Load Mode Register Cycle ................................... 31
Figure 24. SDRAM Controller Timing Diagram - Burst Write Cycle .................................................. 32
Figure 25. SDRAM Controller Timing Diagram - Burst Read Cycle ................................................. 33
Figure 26. SDRAM Controller Timing Diagram - Auto Refresh Cycle .............................................. 34
Figure 27. SPI Control with External Memory - 144 Pin Package .................................................... 39
Figure 28. Intel® Parallel Control Mode - 144 Pin Package .............................................................. 40
Figure 29. Motorola® Parallel Control Mode - 144 Pin Package ....................................................... 41
Figure 30. SPI Write Flow Diagram for DSPAB ................................................................................ 43
Figure 31. SPI Timing for DSPAB ..................................................................................................... 44
Figure 32. SPI Read Flow Diagram for DSPAB ................................................................................ 45
Figure 33. SPI Write Flow Diagram for DSPC .................................................................................. 46
Figure 34. SPI Timing for DSPC .......................................................................................................47
Figure 35. SPI Read Flow Diagram for DSPC .................................................................................. 48
Figure 36. Intel Mode, One-Byte Write Flow Diagram for DSPAB .................................................... 53
Figure 37. Intel Mode, One-Byte Read Flow Diagram for DSPAB ................................................... 54
Figure 38. Motorola Mode, One-Byte Write Flow Diagram for DSPAB ............................................ 55
Figure 39. Motorola Mode, One-Byte Read Flow Diagram for DSPAB ............................................ 55
Figure 40. Typical Parallel Host Mode Control Write Sequence Flow Diagram for DSPAB ............. 56
Figure 41. Typical Parallel Host Mode Control Read Sequence Flow Diagram for DSPAB ............. 57



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