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STM8AF528ATAY データシート(PDF) 78 Page - STMicroelectronics |
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STM8AF528ATAY データシート(HTML) 78 Page - STMicroelectronics |
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78 / 114 page  Electrical characteristics STM8AF52/62xx, STM8AF51/61xx 78/114 DocID14395 Rev 10 Figure 37. Typical NRST pull-up resistance RPU vs VDD Figure 38. Typical NRST pull-up current Ipu vs VDD The reset network shown in Figure 39 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below VIL(NRST) max (see Table 41: NRST pin characteristics), otherwise the reset is not taken into account internally. For power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry, attention must be taken to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. Minimum recommended capacity is 10 nF. |
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