MAS3690CD datasheet(12/41 Pages) DYNEX

12 / 41 page

MA3690/1/3

12/41

Word Count Low

This bit shall be reset to logic zero by the reception of any

valid command word with the exception of TSW, TLC and

TBW.

This bit shall be set to logic one if fewer valid data words

are received than specified by the preceding command word.

Word Count High

This bit shall be rest to logic zero by the reception of any

valid command word with the exception of TSW, TLC and

TBW.

This bit shall be set to logic one if the received message is

longer than stipulated by the preceeding command word.

Illegal Broadcast

This bit shall be reset to logic zero by the reception of any

valid command word with the exception of TSW, TLC and

TBW.

This bit shall be set to logic one if a valid command word

which by definition requires terminal transmission is received

with the broadcast address.

Bus 0 Shutdown

This bit shall be set to logic one if bus 0 is shutdown.

Bus 1 Shutdown

This bit shall be set to logic one if bus 1 is shutdown.

Terminal Flag Inhibited

This bit shall be set to logic one if the internal terminal flag

inhibit is set.

Transmitter Timeout on Bus 0

This bit shall be set to logic one if a transmitter timeout has

occured on bus 0.

Transmitter Timeout on Bus 1

This bit shall be set to logic one if a transmitter timeout has

occured on bus 1.

Note: RTAD0, RTAD1, RTAD2, RTAD3, RTAD4 define the RT

address RTADPAR odd parity with the address bits

BCSTEN0 - Broadcast enable for BUS0

BCSTEN1 - Broadcast enable for BUS1

Figure 4: Subsystem RT Address Buffer

RTAD0

RTAD1

RTAD2

RTAD3

RTAD4

RTADPAR

BUFFER

BCSTEN0

BCSTEN1

ADEN

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